On Wed, Jun 5, 2019 at 4:36 PM Sebastian Huber <sebastian.hu...@embedded-brains.de> wrote: > > On 05/06/2019 12:20, Sachin Ghadi wrote: > > Thanks Sebastian, > > > > On Wed, Jun 5, 2019 at 10:41 AM Sebastian Huber > > <sebastian.hu...@embedded-brains.de> wrote: > >> Hello Sachin, > >> > >> On 05/06/2019 06:15, sachin.gh...@sifive.com wrote: > >>> Hi RTEMS dev team, > >>> > >>> I don’t know if I should send this query to users list or developer list. > >>> > >>> I am working on the getting RTEMS BSP ported on the one of RISC-V > >>> based SoC. > >>> > >>> Current RTEMS has support only for Spike simulator. > >>> > >> we have also support for Qemu. At least at some point in time it worked > >> with a non-upstream Qemu. I am not sure how far the upstreaming of the > >> Qemu support progressed in the last months. > >> > >>> It looks like RTEMS does not fit very well on the systems having less RAM. > >>> > >>> We have 64K of RAM on our standard FPGA development kit for our E > >>> series embedded cores. > >>> > >> 64KiB for code and data is a challenge for RTEMS. You have to tinker > >> with the configuration and reduce the feature set to get into this range. > >> > > Yes 64K is challenge,for both data and code. > > I can use external xip flash for code and but I need to change linker > > script and start up code to load data section from flash to RAM. > > I see RTEMs uses some initialized global variables. > > We have to adjust > > bsps/riscv/riscv/start/linkcmds.in > > so that a ROM can be optionally used for text and read-only data.
Yes Aagree. > > > > > > >>> All of the RTEMS test does not fit within this given RAM and linker > >>> throws error. > >>> > >>> Regarding this I have few questions > >>> > >>> 1. Does RTEMS accept support for new core with limited tests passing? > >>> Or one need full test suit passing to qualify complete test? > >>> > >> What do you mean with "new core"? I think we already support the > >> practically relevant ISA combinations: > > I guess 'core' is wrong word I used..I mean new BSP for our RISCV > > based hardware development kit(Arty100). Core is rv32imac. > > The current BSP uses a device tree for initialization. Do you want to > use this also for this tiny system? If not, then we have to find a way > to initialize everything with a static configuration. > I have device tree blob statically linked as part of bsp `rtems\bsps\riscv\frdm310atry\dts` We are thinking of increasing memory of this FPGA development kit OR have DDR integrated within system. So there is not issue with memory. > -- > Sebastian Huber, embedded brains GmbH > > Address : Dornierstr. 4, D-82178 Puchheim, Germany > Phone : +49 89 189 47 41-16 > Fax : +49 89 189 47 41-09 > E-Mail : sebastian.hu...@embedded-brains.de > PGP : Public key available on request. > > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. > -- Thanks and Regards, Sachin Ghadi _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
