open a bug at http://bugs.xfree86.org/ and include your patch so that
it doesn't get lost. hopefully it will get fixed up and integrated.
Alex
--- �������_��� <[EMAIL PROTECTED]> wrote:
> With the attached trivial patch I forced these cards to work to some
> extent
> with XFree 4.3.0 ...
>
> Only 8,16 bit depths work.
> 64V2/DX may be needed slow_dram_refresh option.
>
> diff -u s3.bak/s3_driver.c s3/s3_driver.c
> --- s3.bak/s3_driver.c 2003-02-27 22:59:43 +0200
> +++ s3/s3_driver.c 2003-07-02 18:24:02 +0300
> @@ -127,11 +127,13 @@
>
> /* supported chipsets */
> static SymTabRec S3Chipsets[] = {
> - { PCI_CHIP_964_0, "964-0"},
> - { PCI_CHIP_964_1, "964-1"},
> - { PCI_CHIP_968, "968" },
> - { PCI_CHIP_TRIO, "Trio32/64" },
> - { PCI_CHIP_AURORA64VP, "Aurora64V+" },
> + { PCI_CHIP_964_0, " 964-0"},
> + { PCI_CHIP_964_1, "964-1"},
> + { PCI_CHIP_968, "968" },
> + { PCI_CHIP_TRIO, "Trio32/64" },
> + { PCI_CHIP_AURORA64VP, "Aurora64V+" },
> + { PCI_CHIP_TRIO64UVP, "Trio64UV+" },
> + { PCI_CHIP_TRIO64V2_DXGX, "Trio64V2/DX/GX" },
> { -1, NULL }
> };
>
> @@ -142,6 +144,8 @@
> { PCI_CHIP_968, PCI_CHIP_968, RES_SHARED_VGA },
> { PCI_CHIP_TRIO, PCI_CHIP_TRIO, RES_SHARED_VGA },
> { PCI_CHIP_AURORA64VP, PCI_CHIP_AURORA64VP,
> RES_SHARED_VGA },
> + { PCI_CHIP_TRIO64UVP, PCI_CHIP_TRIO64UVP, RES_SHARED_VGA
> },
> + { PCI_CHIP_TRIO64V2_DXGX, PCI_CHIP_TRIO64V2_DXGX,
> RES_SHARED_VGA },
> { -1, -1, RES_UNDEFINED }
> };
>
> @@ -531,6 +535,8 @@
> case PCI_CHIP_AURORA64VP: /* ??? */
> pS3->S3NewMMIO = FALSE;
> break;
> + case PCI_CHIP_TRIO64V2_DXGX:
> + case PCI_CHIP_TRIO64UVP:
> case PCI_CHIP_968:
> pS3->S3NewMMIO = TRUE;
> break;
> @@ -580,6 +586,15 @@
> outb(0x102, 0x01);
> outb(0x46e8, 0x08);
>
> + if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
> + {
> + outb (0x3d4, 0x86);
> + outb (0x3d5, 0x80);
> +
> + outb (0x3d4, 0x90);
> + outb (0x3d5, 0x00);
> + }
> +
> if (!pScrn->videoRam) {
> /* probe videoram */
> outb(vgaCRIndex, 0x36);
> @@ -1118,7 +1133,9 @@
>
> if (pS3->Chipset == PCI_CHIP_968)
> shift = 1; /* XXX IBMRGB */
> - else if (pS3->Chipset == PCI_CHIP_TRIO)
> + else if (pS3->Chipset == PCI_CHIP_TRIO ||
> + pS3->Chipset == PCI_CHIP_TRIO64UVP ||
> + pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
> shift = -(pS3->s3Bpp >> 1);
>
> return shift;
> diff -u s3.bak/s3.h s3/s3.h
> --- s3.bak/s3.h 2002-12-11 19:30:47 +0200
> +++ s3/s3.h 2003-06-27 12:40:22 +0300
> @@ -240,6 +240,8 @@
> #define S3_964_SERIES() ((pS3->Chipset == PCI_CHIP_964_0) ||
> \
> (pS3->Chipset == PCI_CHIP_964_1))
> #define S3_TRIO_SERIES() ((pS3->Chipset == PCI_CHIP_TRIO) ||
> \
> - (pS3->Chipset == PCI_CHIP_AURORA64VP))
> + (pS3->Chipset == PCI_CHIP_AURORA64VP) || \
> + (pS3->Chipset == PCI_CHIP_TRIO64UVP) || \
> + (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX))
>
> #endif /* _S3_H */
> diff -u s3.bak/s3_Trio64DAC.c s3/s3_Trio64DAC.c
> --- s3.bak/s3_Trio64DAC.c 2003-02-27 22:59:43 +0200
> +++ s3/s3_Trio64DAC.c 2003-07-02 17:40:30 +0300
> @@ -324,9 +324,13 @@
> if (pS3->Chipset == PCI_CHIP_AURORA64VP)
> S3TrioSetClock(pScrn, mode->Clock, 2, 1, 1, 63, 0, 3, 2,
> 135000, 270000);
> + else if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
> + S3TrioSetClock(pScrn, mode->Clock, 2, 1, 1, 31, 0, 3, 2,
> + 170000, 270000);
> else
> S3TrioSetClock(pScrn, mode->Clock, 2, 1, 1, 31, 0, 3, 2,
> 135000, 270000);
> +
>
> outb(0x3c4, 1);
> blank = inb(0x3c5);
> @@ -347,6 +351,11 @@
> sr18 = inb(0x3c5) & ~0x80;
> outb(pS3->vgaCRIndex, 0x33);
> cr33 = inb(pS3->vgaCRReg) & ~0x28;
> +
> + if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
> + {
> + cr33 |= 0x20;
> + }
>
> /* ! pixmux */
> switch (pScrn->depth) {
>
>
> _______________________________________________
> Devel mailing list
> [EMAIL PROTECTED]
> http://XFree86.Org/mailman/listinfo/devel
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