On Thu, 3 Jul 2003, Alex Deucher wrote:
>Date: Thu, 3 Jul 2003 07:10:09 -0700 (PDT)
>From: Alex Deucher <[EMAIL PROTECTED]>
>To: [EMAIL PROTECTED]
>Reply-To: [EMAIL PROTECTED]
>Content-Type: text/plain; charset=us-ascii
>Subject: Re: S3 Trio64UV+, S3 Trio64V2/DX
>
>open a bug at http://bugs.xfree86.org/ and include your patch so that
>it doesn't get lost. hopefully it will get fixed up and integrated.
Be sure to regenerate the patch without gratuitous whitespace
changes though.
>> Only 8,16 bit depths work.
>> 64V2/DX may be needed slow_dram_refresh option.
>>
>> diff -u s3.bak/s3_driver.c s3/s3_driver.c
>> --- s3.bak/s3_driver.c 2003-02-27 22:59:43 +0200
>> +++ s3/s3_driver.c 2003-07-02 18:24:02 +0300
>> @@ -127,11 +127,13 @@
>>
>> /* supported chipsets */
>> static SymTabRec S3Chipsets[] = {
>> - { PCI_CHIP_964_0, "964-0"},
>> - { PCI_CHIP_964_1, "964-1"},
>> - { PCI_CHIP_968, "968" },
>> - { PCI_CHIP_TRIO, "Trio32/64" },
>> - { PCI_CHIP_AURORA64VP, "Aurora64V+" },
>> + { PCI_CHIP_964_0, " 964-0"},
^^^^^^^^^
is that necessary?
>> + { PCI_CHIP_964_1, "964-1"},
>> + { PCI_CHIP_968, "968" },
>> + { PCI_CHIP_TRIO, "Trio32/64" },
>> + { PCI_CHIP_AURORA64VP, "Aurora64V+" },
>> + { PCI_CHIP_TRIO64UVP, "Trio64UV+" },
>> + { PCI_CHIP_TRIO64V2_DXGX, "Trio64V2/DX/GX" },
>> { -1, NULL }
>> };
>>
>> @@ -142,6 +144,8 @@
>> { PCI_CHIP_968, PCI_CHIP_968, RES_SHARED_VGA },
>> { PCI_CHIP_TRIO, PCI_CHIP_TRIO, RES_SHARED_VGA },
>> { PCI_CHIP_AURORA64VP, PCI_CHIP_AURORA64VP,
>> RES_SHARED_VGA },
>> + { PCI_CHIP_TRIO64UVP, PCI_CHIP_TRIO64UVP, RES_SHARED_VGA
>> },
>> + { PCI_CHIP_TRIO64V2_DXGX, PCI_CHIP_TRIO64V2_DXGX,
>> RES_SHARED_VGA },
>> { -1, -1, RES_UNDEFINED }
>> };
>>
>> @@ -531,6 +535,8 @@
>> case PCI_CHIP_AURORA64VP: /* ??? */
>> pS3->S3NewMMIO = FALSE;
>> break;
>> + case PCI_CHIP_TRIO64V2_DXGX:
>> + case PCI_CHIP_TRIO64UVP:
>> case PCI_CHIP_968:
>> pS3->S3NewMMIO = TRUE;
>> break;
>> @@ -580,6 +586,15 @@
>> outb(0x102, 0x01);
>> outb(0x46e8, 0x08);
>>
>> + if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
>> + {
>> + outb (0x3d4, 0x86);
>> + outb (0x3d5, 0x80);
>> +
>> + outb (0x3d4, 0x90);
>> + outb (0x3d5, 0x00);
These should not be hard coded register values.
>> + }
>> +
>> if (!pScrn->videoRam) {
>> /* probe videoram */
>> outb(vgaCRIndex, 0x36);
>> @@ -1118,7 +1133,9 @@
>>
>> if (pS3->Chipset == PCI_CHIP_968)
>> shift = 1; /* XXX IBMRGB */
>> - else if (pS3->Chipset == PCI_CHIP_TRIO)
>> + else if (pS3->Chipset == PCI_CHIP_TRIO ||
>> + pS3->Chipset == PCI_CHIP_TRIO64UVP ||
>> + pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX)
>> shift = -(pS3->s3Bpp >> 1);
>>
>> return shift;
>> diff -u s3.bak/s3.h s3/s3.h
>> --- s3.bak/s3.h 2002-12-11 19:30:47 +0200
>> +++ s3/s3.h 2003-06-27 12:40:22 +0300
>> @@ -240,6 +240,8 @@
>> #define S3_964_SERIES() ((pS3->Chipset == PCI_CHIP_964_0) ||
>> \
>> (pS3->Chipset == PCI_CHIP_964_1))
>> #define S3_TRIO_SERIES() ((pS3->Chipset == PCI_CHIP_TRIO) ||
>> \
>> - (pS3->Chipset == PCI_CHIP_AURORA64VP))
>> + (pS3->Chipset == PCI_CHIP_AURORA64VP) || \
>> + (pS3->Chipset == PCI_CHIP_TRIO64UVP) || \
>> + (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX))
Again, a bit of gratuitous whitespace change. I'd tidy all of
these things up before submitting to increase the chance of it
being committed.
Hope this helps.
--
Mike A. Harris
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