On Wed, 2003-08-27 at 06:15, Egbert Eich wrote:
> Appearantly there are still issues with VGA framebuffer and emulated
> PIO register writes when saving and restoring fonts. These problems
> only affect certain cards (so far I've only heared of Nvidia cards).
> Mark Vojkovich is sure that these are related to caching problems,
> too.
>
> Have you made any progress investigating this issue?
I have looked at this, here is what I know (or think I know :-)
* The vga font save/restore seems unrelated to caching.
- The vga framebuffer (where the fonts live) has always been mapped non-cached.
The EFI on HP ZX1 would also have set this region up as non-cached.
We have verified by inspecting the TLB it is non-cached.
The kernel patch for non-caching (should not have mattered given the above)
does not affect the font/save restore, nor did I expect it to.
Everything seems right.
* The vga font save/restore seems related to timing, specifically too many
back to back bus transactions to the VGA framebuffer.
- Adding more delays into SlowBCopy makes the problem go away.
- The symptom of the problem is the bridge appears to be in a master
abort error state. This would occur if the vga did not respond fast
enough.
* So far we've only seen this problem with nvidia (but see next item).
- This suggests the problem is specific to the nvidia vga implementation
and the speed at which it responds.
* SlowBCopy seems only to be used for VGA font/save restore.
- The whole idea of SlowBCopy bothers me from a technical perspective.
- SlowBCopy has been around a while, thus this is not the first time
folks have run into this problem.
- No one seem to know anymore when or why its needed, but it seems to have
first appeared on DEC ALPHA systems and seem unnecessary on standard PC
class machines. It is an interesting correlation that both ALPHA and IA64
had fast bus transaction design goals.
Mark, is there a hardware engineer at nvidia that would be familar with
the VGA timing? Is it possible your VGA is running near or beyond the
limits of the PCI timing requirements? My understanding is the ZX1 is a
very aggressive chipset tuned for high performance, so its possible on a
standard PC you may not have seen the timing problems, even if you were
close to the limits.
John
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