On Thu, 2003-08-28 at 16:40, Marc Aurele La France wrote: > > ... which basically means that framebuffers cannot benifit from CPU > > caching. I don't beleive this to be the case. > > Further to this, it appears you don't realise that the frambuffers we're > talking about here, _are_ in PCI space.
Yes, I realize framebuffers are in PCI space. All I can do is make the following observations: 1) I was told by HP: "The ZX1 chipset doesn't support cacheable access to any MMIO space, regardless of whether that space happens to contain RAM, ROM, device CSRs, etc." This statement seems clear to me, do you have a different interpretation? 2) Write combining is a typical memory attribute to apply to a framebuffer, on the IA64 the write combining memory attribute is also non-cacheable. 3) Would you really want caching on framebuffer memory in the presence of a graphics co-processor that can alter the memory independently of the cache? 4) It does not seem outlandish when considering the universe of PCI devices to believe the memory regions on these devices either have side-effects or can be modified by the device, either case would demand non-caching. It would be very hard, as it has been pointed out, for the firmware to know what memory regions on a device could be cached safely. Thus a decision to treat any PCI memory region as non-cached sounds like a plausible design decision. _______________________________________________ Devel mailing list [EMAIL PROTECTED] http://XFree86.Org/mailman/listinfo/devel
