On 3/10/07, bruno schwander <[EMAIL PROTECTED]> wrote:
I looked at that diff and it looks like what I added, except that I also set bits 7:6 of CCR68 to 01 because the doc I have says that will select VCLK from the programmable VCLK regs, CCR6C and CCR6D.
I fixed the vclk problem. The postscalar shift was wrong in SMI_CalcClocks(). either grab my updated tree or change the shift from 6 to 7. Alex _______________________________________________ Devel mailing list Devel@XFree86.Org http://XFree86.Org/mailman/listinfo/devel
