On 3/12/07, bruno schwander <[EMAIL PROTECTED]> wrote:
I used your vclk setting code as in smi_driver.c, and changed the shift
in SMI_CommonCalcClock() but it seems to still have some
issue.
12220 clock gives me values of
SR6C: 63, SR6D: 1D
That's going to give you a vclk of ~48.88 Mhz
Unfortunately, the min clock on the smi is 20 Mhz (although I'd think
you should be able to get down to at least the reference clock), so
that may be causing a problem in the calculation function. If you
want to calculate the clock yourself you can use the following
formula:
VCLK = 14.31818 Mhz * (VNR/VDR) * (1/(1 + PS))
VNR being SR6C and VDR and SR6D. PS is bit 7 of SR6D.
I hope this helps.
Alex
bruno
On Sun, 11 Mar 2007, Alex Deucher wrote:
> On 3/10/07, bruno schwander <[EMAIL PROTECTED]> wrote:
>> I looked at that diff and it looks like what I added, except that I also
>> set bits 7:6 of CCR68 to 01 because the doc I have says that will select
>> VCLK from the programmable VCLK regs, CCR6C and CCR6D.
>>
>
> I fixed the vclk problem. The postscalar shift was wrong in
> SMI_CalcClocks(). either grab my updated tree or change the shift
> from 6 to 7.
>
> Alex
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