On Tue, 2011-09-13 at 08:43 +0200, Arnd Bergmann wrote: > On Monday 12 September 2011 19:20:35 Mark Salter wrote: > > On Mon, 2011-09-12 at 14:11 -0600, Grant Likely wrote: > > > On Wed, Aug 31, 2011 at 05:26:41PM -0400, Mark Salter wrote: > > > > + interrupt-controller; > > > > + #interrupt-cells = <1>; > > > > + compatible = "ti,c64x+core-pic"; > > > > > > The interrupt controller isn't addressable? Is it integrated into > > > the CPU? > > > > Yes, that core controller is controlled through registers accessed > > with special-purpose instructions, not MMIO. Other controllers, like > > megamodule and some as-yet unimplemented use MMIO. > > Are these instructions specific to the interrupt controller or > do they access a register space that can contain arbitrary > devices? > > If there is a separate address space for special devices, it might > be good to describe that in the device tree, like we do for PCI > I/O space. >
It is a core register area. Similar to ARM or MIPS coprocessor registers. --Mark _______________________________________________ devicetree-discuss mailing list [email protected] https://lists.ozlabs.org/listinfo/devicetree-discuss
