On Tue, 2011-09-13 at 11:54 -0600, Grant Likely wrote: > On Tue, Sep 13, 2011 at 9:33 AM, Arnd Bergmann <[email protected]> wrote: > > On Tuesday 13 September 2011, Mark Salter wrote: > >> On Tue, 2011-09-13 at 08:43 +0200, Arnd Bergmann wrote: > >> > Are these instructions specific to the interrupt controller or > >> > do they access a register space that can contain arbitrary > >> > devices? > >> > > >> > If there is a separate address space for special devices, it might > >> > be good to describe that in the device tree, like we do for PCI > >> > I/O space. > >> > > >> > >> It is a core register area. Similar to ARM or MIPS coprocessor > >> registers. > > > > I guess it still depends, it's probably a grey area. If the register layout > > is the same on all c6x cores and it's only for core stuff, there is no need > > to put it in the device tree. If you have multiple soc (off-core) devices > > being controlled through the registers, or the numbers vary a lot between > > different chips, I would put all of them into the device tree. > > It's an interrupt controller. There still needs to be a node to act > as the interrupt-parent and specify #interrupt-cells.
It already has that. But maybe that node should be moved into the cpu node. --Mark _______________________________________________ devicetree-discuss mailing list [email protected] https://lists.ozlabs.org/listinfo/devicetree-discuss
