From: Shiraz Hashim <[email protected]>

SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
Cell spi controller through its system registers, which otherwise remains under
PL022 control which some protocols do not want.

This patch adds spics controller nodes in device tree for various SPEAr13xx
SoCs.

Cc: Linus Walleij <[email protected]>
Signed-off-by: Shiraz Hashim <[email protected]>
Reviewed-by: Vipin Kumar <[email protected]>
Signed-off-by: Viresh Kumar <[email protected]>
---
 arch/arm/boot/dts/spear1310.dtsi | 12 ++++++++++++
 arch/arm/boot/dts/spear1340.dtsi | 14 ++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 419ea74..d5661ee 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -17,6 +17,18 @@
        compatible = "st,spear1310";
 
        ahb {
+               spics: spics@e0700000{
+                       compatible = "st,spear-spics-gpio";
+                       reg = <0xe0700000 0x1000>;
+                       st-spics,peripcfg-reg = <0x3b0>;
+                       st-spics,sw-enable-bit = <12>;
+                       st-spics,cs-value-bit = <11>;
+                       st-spics,cs-enable-mask = <3>;
+                       st-spics,cs-enable-shift = <8>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+               };
+
                ahci@b1000000 {
                        compatible = "snps,spear-ahci";
                        reg = <0xb1000000 0x10000>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index d71fe2a..1604425 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -17,6 +17,20 @@
        compatible = "st,spear1340";
 
        ahb {
+
+               spics: spics@e0700000{
+                       compatible = "st,spear-spics-gpio";
+                       reg = <0xe0700000 0x1000>;
+                       st-spics,peripcfg-reg = <0x42c>;
+                       st-spics,sw-enable-bit = <21>;
+                       st-spics,cs-value-bit = <20>;
+                       st-spics,cs-enable-mask = <3>;
+                       st-spics,cs-enable-shift = <18>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       status = "disabled";
+               };
+
                ahci@b1000000 {
                        compatible = "snps,spear-ahci";
                        reg = <0xb1000000 0x10000>;
-- 
1.7.12.rc2.18.g61b472e

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