On Tue, Jun 18, 2013 at 08:59:03PM +0200, Sebastian Hesselbarth wrote:
> >S = 0 means 4 bit I, 8 bit A
> >S = F means special
> >S = 1 could mean 16 bit I, etc , etc
>
> S & 0x8 == 0x0 means 7b target
> S & 0x8 == 0x8 means 7b special ?
No need, special == mbus driver defined. There is no target ID.
The forms could be:
0IAA0000
FK000000
- K=0 -> internal regs
- K=1 -> PCI-E thingy
etc
1IIAA000 (future expansion example)
> >The mbus top level ranges remap already supports>4G locations for
> >the windows, even though current hardware cannot do that.
>
> True. But as Arnd also mentioned, I don't think it will ever be a
> problem at all. Possibly there will never be any future SoC with mbus
> that will either allow >32b remap base addresses nor >4G size.
Actually, I think the failure to allow > 32b remap is a mistake
on Marvell's part. Linux needs as much low memory as possible, moving
things above 4G gives you more low SDRAM.
So I'd hope to see 40bit addressing for MBUS windows in a future chip.
But again, that already works with what Ezequiel has..
To be very clear, the only issue with the 32 bit offset is if we need
to describe an offset into a target in DT that is larger than 32
bits. The only use of offsets in DT is for internal regs. The
need for a > 32 bit offset in DT does not exist with the current
architecture.
Jason
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