On Tue, Jul 28, 2015 at 11:38:06AM +0200, Lars-Peter Clausen wrote:
> + active = axi_dmac_active_desc(chan);
> + if (!active)
> + return;
> +
> + if (active->cyclic) {
> + vchan_cyclic_callback(&active->vdesc);
> + } else {
> + while (active &&
do you need to check this, you did that few lines back?
> +static struct axi_dmac_desc *axi_dmac_alloc_desc(unsigned int num_sgs)
> +{
> + struct axi_dmac_desc *desc;
> +
> + desc = kzalloc(sizeof(struct axi_dmac_desc) +
> + sizeof(struct axi_dmac_sg) * num_sgs, GFP_ATOMIC);
we recommend GFP_NOWAIT for these...
> +static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg(
> + struct dma_chan *c, struct scatterlist *sgl,
> + unsigned int sg_len, enum dma_transfer_direction direction,
> + unsigned long flags, void *context)
> +{
> + struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
> + struct axi_dmac_desc *desc;
> + struct scatterlist *sg;
> + unsigned int i;
> +
> + if (direction != chan->direction)
are the channels unidirectional
> + return NULL;
> +
> + desc = axi_dmac_alloc_desc(sg_len);
> + if (!desc)
> + return NULL;
> +
> + for_each_sg(sgl, sg, sg_len, i) {
> + if (!axi_dmac_check_addr(chan, sg_dma_address(sg)) ||
> + !axi_dmac_check_len(chan, sg_dma_len(sg))) {
> + kfree(desc);
> + return NULL;
> + }
> +
> + if (direction == DMA_DEV_TO_MEM)
> + desc->sg[i].dest_addr = sg_dma_address(sg);
> + else
> + desc->sg[i].src_addr = sg_dma_address(sg);
where is device side programming ?
> +
> + if (axi_dmac_dest_is_mem(chan) && axi_dmac_src_is_mem(chan))
> + chan->direction = DMA_MEM_TO_MEM;
> + else if (!axi_dmac_dest_is_mem(chan) && axi_dmac_src_is_mem(chan))
> + chan->direction = DMA_MEM_TO_DEV;
> + else if (axi_dmac_dest_is_mem(chan) && !axi_dmac_src_is_mem(chan))
> + chan->direction = DMA_DEV_TO_MEM;
> + else
> + chan->direction = DMA_DEV_TO_DEV;
ok this seems to answer my other question but is this something we are
specifying in SW or capability of a channel?
--
~Vinod
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