Add quirk for phy interface of MIPS-based chipsets. The ARM-based chipsets have four phy interface control registers and each port has two registers but the MIPS-based chipsets have three. There are no information and documentation.
The Broadcom strict-ahci based BSP of legacy version did not control these registers. Signed-off-by: Jaedon Shin <[email protected]> --- drivers/ata/ahci_brcmstb.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c index 194aeda8f14d..5098e6c041ac 100644 --- a/drivers/ata/ahci_brcmstb.c +++ b/drivers/ata/ahci_brcmstb.c @@ -71,6 +71,7 @@ enum brcm_ahci_quirks { BRCM_AHCI_QUIRK_NONCQ = BIT(0), + BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1), }; struct brcm_ahci_priv { @@ -119,6 +120,9 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port) void __iomem *p; u32 reg; + if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE) + return; + /* clear PHY_DEFAULT_POWER_STATE */ p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; reg = brcm_sata_readreg(p); @@ -148,6 +152,9 @@ static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port) void __iomem *p; u32 reg; + if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE) + return; + /* power-off the PHY digital logic */ p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; reg = brcm_sata_readreg(p); @@ -297,8 +304,10 @@ static int brcm_ahci_probe(struct platform_device *pdev) if (IS_ERR(priv->top_ctrl)) return PTR_ERR(priv->top_ctrl); - if (of_device_is_compatible(dev->of_node, "brcm,bcm7425-ahci")) + if (of_device_is_compatible(dev->of_node, "brcm,bcm7425-ahci")) { priv->quirks |= BRCM_AHCI_QUIRK_NONCQ; + priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE; + } brcm_sata_quirks(pdev, priv); -- 2.6.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
