Add a device node for the L2 cache, and link the CPU nodes to it. The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways).
Signed-off-by: Geert Uytterhoeven <[email protected]> --- What are the DT bindings for a Cortex-A7 L2 cache controller? v2: - Drop (incorrect) optional cache-{size,sets,{block,line}-size} properties, as this information is auto-detected, - Integrate linking CPUs to L2 cache into this patch, - Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add SYSC PM Domain DT Support". --- arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 56acafbb70dc7bc9..1b53495b9c95611c 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -40,6 +40,7 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; + next-level-cache = <&L2_CA7>; }; cpu1: cpu@1 { @@ -47,9 +48,16 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + next-level-cache = <&L2_CA7>; }; }; + L2_CA7: cache-controller@1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
