On Thu, Jun 01, 2017 at 12:20:53AM +0100, Russel Winder via Digitalmars-d-learn wrote: [...] > However, I note here that the Chapel folk are taking a quite > interesting view of algorithm implementation in the Benchmarks Game. > They are totally eschewing "heroic implementations" such as all the C, > C++, etc. in favour of understandable and simple ones. Their take on > raw performance is "if you need it to go faster, use a bigger > computer". Which is quite easy when you have a number of Cray > computers at your disposal. :-) Whilst having some fun, the > Benchmark's Game has become all about heroic implementations on a > specific computer. Which makes the Chapel line an excellent one. > > OK for wc the case is different because it is about performance on the > users computer. But still I like the "keep the implementation > comprehensible, avoid heroic implementation". [...]
With D, we can have the cake and eat it too. The understandable / naïve implementation can be available as a fallback (and reference implementation), with OS-specific optimized implementations guarded under version() or static-if blocks so that one could, in theory, provide implementations specific to each supported platform that would give the best performance. I disagree about the philosophy of "if you need to go faster, use a bigger computer". There are some inherently complex problems (such as NP-complete, PSPACE-complete, or worse, outright exponential class problems) where the difference between a "heroic implementation" of a computational primitive and a naïve one may mean the difference between obtaining a result in this lifetime vs. practically never. Or, more realistically speaking, the difference between being able to solve moderately-complex problem instances vs. being able to solve only trivial toy instances. When you're dealing with exponential complexity, every small bit counts, and you can never get a big enough computer. An even more down-to-earth counterargument is that if CPU vendors had been content with understandable, simple CPU implementations, and eschewed "heroic", hard-to-understand things like instruction pipelines and cache hierarchies, we'd still be stuck with 16 MHz CPU's in 2017. T -- Not all rumours are as misleading as this one.
