Tue, 05 Oct 2010 20:49:34 +0200, Tomek Sowiński wrote: > I've been reading about caching mechanisms in today's processors -- > amazing in their intricacy. > It made me wonder, is there a way to exclude immutable regions of memory > from a cache coherence mechanism? I mean, let the processor know: no > invalidation for cache lines from immutable memory. > And even if it's possible, how much would it really help? I have no > intuition about how expensive those coherence mechanisms are. > > CPU geeks speak up! :)
What generation of CPUs are you talking about? Based on discussions here, it seems people like Nick S. are still using single core, single socket PII/PIII class systems. The Opteron/Xeon systems look like NUMA systems and consumer systems use the simpler FSB. I don't know about other architectures.
