Tomek Sowiński wrote:
I've been reading about caching mechanisms in today's processors -- amazing in their
intricacy.
It made me wonder, is there a way to exclude immutable regions of memory from a cache
coherence mechanism? I mean, let the processor know: no invalidation for cache lines from
immutable memory.
And even if it's possible, how much would it really help? I have no intuition about how
expensive those coherence mechanisms are.
CPU geeks speak up! :)
Based on my reading of AMD's docs, it should happen automatically.
The cache lines will be marked as 'exclusive' when the first core reads
them, and will change to 'shared' when other cores read them.
Whenever a new core accesses that memory, it will ALWAYS get it from the
main memory, never from the other cores.
As far as I know, the cost for cache coherency comes when core-to-core
transfer is required.
