What's up everybody,
I'm writing an r200/r300 driver for my small OS,
to be honest it's based (a lot) on your driver and linux's fb.
The thing is I managed to get blitting to work.
my hardware:
P4 2GHz, intel 945D
Gigabyte Radeon 9550 128MB/128bit (GV-R955128D) by linux (gentoo 2.6.17-ck1-r3)
seen as:
//01:00.0 0300: 1002:4153
01:00.0 VGA compatible controller: ATI Technologies Inc RV350 AS [Radeon 9550]
(prog-if 00 [VGA])
// Subsystem: 1458:4050
Subsystem: Giga-byte Technology Unknown device 4050
Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 11
Memory at d8000000 (32-bit, prefetchable) [size=128M]
I/O ports at d800 [size=256]
Memory at c7800000 (32-bit, non-prefetchable) [size=64K]
Expansion ROM at d7fe0000 [disabled] [size=128K]
Capabilities: [58] AGP version 2.0
Capabilities: [50] Power Management version 2
//01:00.1 0380: 1002:4173
01:00.1 Display controller: ATI Technologies Inc RV350 ?? [Radeon 9550]
(Secondary)
// Subsystem: 1458:4051
Subsystem: Giga-byte Technology Unknown device 4051
Flags: bus master, 66MHz, medium devsel, latency 64
Memory at c8000000 (32-bit, prefetchable) [size=128M]
Memory at c7000000 (32-bit, non-prefetchable) [size=64K]
Capabilities: [50] Power Management version 2
When the driver prepares for blitting
setting reg R300_VAP_UNKNOWN_221C to R300_221C_CLEAR istead of NORMAL
fixed the problem of nothing happening.
Reg R300_RS_CNTL_0 should be set to
(1 << R300_RS_CNTL_TC_CNT_SHIFT) | (0 << R300_RS_CNTL_CI_CNT_SHIFT)
Also setting R300_VTX_ST_DENORMALIZED in R300_SE_VTE_CNTL
doesn't have any effect.
When setting the source I had to set reg R300_TX_PITCH_0 to
Image Width - 8
instead of
Image Pitch - 64
And R300_TX_OFFSET_0 to
(Image Offset/*in bytes*/ / 32) << dDFB_R300_TXO_OFFSET_SHIFT
instead of
Image Offset/*in bytes*/ << dDFB_R300_TXO_OFFSET_SHIFT
With these changes everything works good, at least for me;p
I also decoded the vertex program using macros from vertex_shader.h from dri's
r300 driver
//R300_VAP_PVS_CNTL_1 = 0x00401000
R300_VAP_PVS_CNTL_1 = (0 << dDFB_R300_PVS_CNTL_1_PROGRAM_START_SHIFT)
| (4 << dDFB_R300_PVS_CNTL_1_POS_END_SHIFT)
| (4 << dDFB_R300_PVS_CNTL_1_PROGRAM_END_SHIFT)
//R300_VAP_PVS_CNTL_2 = 0x00040000
R300_VAP_PVS_CNTL_2 = (0 << dDFB_R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT)
| (4 << dDFB_R300_PVS_CNTL_2_PARAM_COUNT_SHIFT)
//R300_VAP_PVS_CNTL_3 = 0x00000004
R300_VAP_PVS_CNTL_3 = (4 << dDFB_R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT)
| (4 << dDFB_R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT)
/*i think both of them should point to last instruction*/
/*
the rest of the stuf
and just after
R300_VAP_PVS_UPLOAD_ADDRESS = dDFB_R300_PVS_UPLOAD_PROGRAM
*/
R300_VAP_PVS_UPLOAD_DATA = EASY_VSF_OP (MAD, 0, ALL, TMP)
R300_VAP_PVS_UPLOAD_DATA = VSF_ATTR_X (0)
R300_VAP_PVS_UPLOAD_DATA = VSF_PARAM (0)
R300_VAP_PVS_UPLOAD_DATA = EASY_VSF_SOURCE (0, ZERO, ZERO, ZERO, ZERO, PARAM,
NONE)
R300_VAP_PVS_UPLOAD_DATA = EASY_VSF_OP (MAD, 0, ALL, TMP)
R300_VAP_PVS_UPLOAD_DATA = VSF_ATTR_Y (0)
R300_VAP_PVS_UPLOAD_DATA = VSF_PARAM (1)
R300_VAP_PVS_UPLOAD_DATA = VSF_TMP (0)
R300_VAP_PVS_UPLOAD_DATA = EASY_VSF_OP (MAD, 0, ALL, TMP)
R300_VAP_PVS_UPLOAD_DATA = VSF_ATTR_Z (0)
R300_VAP_PVS_UPLOAD_DATA = VSF_PARAM (2)
R300_VAP_PVS_UPLOAD_DATA = VSF_TMP (0)
R300_VAP_PVS_UPLOAD_DATA = EASY_VSF_OP (MAD, 0, ALL, RESULT)
R300_VAP_PVS_UPLOAD_DATA = VSF_ATTR_W (0)
R300_VAP_PVS_UPLOAD_DATA = VSF_PARAM (3)
R300_VAP_PVS_UPLOAD_DATA = VSF_TMP (0)
R300_VAP_PVS_UPLOAD_DATA = EASY_VSF_OP (ADD, 1, ALL, RESULT)
R300_VAP_PVS_UPLOAD_DATA = VSF_REG (1)
R300_VAP_PVS_UPLOAD_DATA = EASY_VSF_SOURCE (1, ZERO, ZERO, ZERO, ZERO, ATTR,
NONE)
R300_VAP_PVS_UPLOAD_DATA = EASY_VSF_SOURCE (1, ZERO, ZERO, ZERO, ZERO, ATTR,
NONE)
I might have missed something, because I was simply trying a lot of different
possibilities and there were a lot of'em;p
Best regards and hope it's helpful,
Timon
PS. you also might play with R300_RS_CNTL_0_UNKNOWN_18 in reg R300_RS_CNTL_0
it doesn't change anything for me but in the reg.h file it's written
// 0_UNKNOWN_18 has always been set except for clear operations.
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