Ga1axy0 opened a new pull request, #19877:
URL: https://github.com/apache/tvm/pull/19877
## Description
This PR adds local RISC-V CPU feature detection for LLVM targets when TVM is
running on RISC-V Linux.
When the target does not explicitly provide `mcpu` or `mattr`, TVM now uses
`riscv_hwprobe` to populate the default LLVM target attributes from the local
machine. This includes the base IMA extensions, F/D, C, and V.
When V is reported by `riscv_hwprobe`, TVM also reads the `vlenb` CSR to
derive the local vector length and adds the matching `zvl*b` attribute, such as
`+zvl256b`.
Explicit `mcpu` and `mattr` still take precedence, so cross-compilation
behavior remains unchanged.
## Testing
Built TVM with LLVM enabled on a RISC-V Linux board and verified that
`llvm_get_cpu_features` detects local features without explicit `mattr`.
```python
from tvm.target import Target
from tvm.target.codegen import llvm_get_cpu_features
target = Target({
"kind": "llvm",
"mtriple": "riscv64-linux-gnu",
"mabi": "lp64d",
"num-cores": 8,
})
print(sorted(llvm_get_cpu_features(target)))
```
On SpacemiT K3 X100, the detected feature set is:
```text
64bit
a
c
d
f
i
m
optimized-nf2-segment-load-store
v
zaamo
zalrsc
zca
zicsr
zmmul
zve32f
zve32x
zve64d
zve64f
zve64x
zvl128b
zvl256b
zvl32b
zvl64b
```
This matches the expected local CPU capabilities. In particular, d is
detected for the lp64d ABI, v is detected for RVV support, and zvl256b reflects
the board's 256-bit vector length as reported through vlenb.
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