tqchen commented on code in PR #19877:
URL: https://github.com/apache/tvm/pull/19877#discussion_r3462438165
##########
src/target/llvm/llvm_instance.cc:
##########
@@ -199,15 +277,31 @@ LLVMTargetInfo::LLVMTargetInfo(LLVMInstance& instance,
if (triple_.empty() || triple_ == "default") {
triple_ = llvm::sys::getDefaultTargetTriple();
}
+ bool has_explicit_mcpu = target.Get("mcpu").has_value();
cpu_ =
target.Get("mcpu").value_or(ffi::String(defaults::cpu)).as_or_throw<ffi::String>();
+ bool has_explicit_mattr = false;
if (const auto& v = (target.Get("mattr"))
.value_or(nullptr)
.as_or_throw<ffi::Optional<ffi::Array<ffi::String>>>()) {
+ has_explicit_mattr = true;
for (const ffi::String& s : v.value()) {
attrs_.push_back(s);
}
}
+
+ llvm::Triple target_triple(triple_);
+ auto arch = target_triple.getArch();
+ llvm::Triple host_triple(llvm::sys::getDefaultTargetTriple());
+ if (!has_explicit_mattr && !has_explicit_mcpu && arch ==
host_triple.getArch() &&
+ target_triple.getOS() == host_triple.getOS() &&
Review Comment:
ideally we don't specialize for riscv here, would it be something that llvm
upstream can do? or can we put some flags in target. and register target tag
which helps cross compile. e.g. register features via something like
https://github.com/apache/tvm/blob/main/python/tvm/target/tag_registry/riscv_cpu.py#L30
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