Ouch! This sounds like some of those previous threads.
>Why do you want 16MS/sec real instead of 8MS/sec complex? > >Eric I didn't want to go there, the part I was worried about is to have no processing since the CIC filter has some unpleasant properties (not very flat, aliasing at the borders). >From my point of view the PC is much more accessible than the FPGA. To get an >understanding of the algorithms I don't have to try to read someones Verilog code, and to change any algorithms I don't have to write Verilog. On the other hand the PC should be quite capable in handling most signal processing tasks. I'm generally interested in working with FPGAs but I don't have a logic analyzer, so that actual experiments might be cumbersome. Anyway, I saw today that there is an fpga version with a halfband filter now, very nice. If you look at the analog part of the two alternatives, I must admit, that if you keep the input bandwidth the same (8MHz), analog filter requirements would be quite relaxed with the normal usrp. Well, well I think I should just stay with what I've got for now. Regards, Kilian _____________________________________________________________________ Der WEB.DE SmartSurfer hilft bis zu 70% Ihrer Onlinekosten zu sparen! http://smartsurfer.web.de/?mc=100071&distributionid=000000000071 _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
