>
> set_rx_freq(-10e6) should work, assuming you've got the mux setup
correctly.
>
> If you're using the first input on the Basic Rx on the A-side you'll
> want set_mux(0xf0f0f0f0)
This is the mux I'm setting, and with set_rx_freq(-10e6) I still have no
luck.
In benchmark_rx.py, the samples are unmodified up to the channel filter,
correct?
>
> The computation that splits the tuning between the RF front end and
> the DDC is done in usrp.py (tune). In the case of basic_rx, the
> daughterboard set_freq returns (True, 0), indicating that DC is at 0
> Hz in the IF. That is, there's nothing to tune on the daughterboard,
> and all the work is done in the DDC.
>
I see, this makes sense.
At this point, I'm not really sure what's going on. I guess we will dig
around the FPGA code, but I still don't understand how we can properly
receive and plot the sine wave if it were broken.
- George
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