Martin Braun wrote: > If you just want to find spectrum holes, you might be able to teach the > FPGA...
*If* you are going to make a custom FPGA build, one could do as follows: Since there are two ADCs operating on quadrature downconverted samples at 64 Msps, the spectral width is actually 64 MHz entering the FPGA. (This is the reason the minimum decimation rate in the CIC/HB chain is 8, in order to reduce the sample rate/frequency content to 8 MHz to fit the USB capacity.) In practice, the anti-aliasing filters on the RFX limit the usable passband width to approximately 50 MHz. So you can cover the whole 2.4 GHz ISM band with two different center frequencies. As discussed in a recent thread, one could collect samples at this full rate in the FPGA for a period of time, stream them to a FIFO, then drain the FIFO at 1/8 the clock rate over the USB. You would be limited to collecting something like 2-4K samples at a maximum duty cycle of 12.5%. The host software would take these time domain "frames", perform windowing, FFT, and bin-over-time smoothing, resulting in a spectral estimate across 50 MHz. This is almost identical to what the existing usrp_fft.py script does, except now the time domain frame decimation would be happening in the FPGA instead of in the host, to operate over the full ADC bandwidth instead of over a maximum of 8 MHz. After "enough" frames have been received, one would switch the center frequency to the second one and repeat. (Much of the above FPGA processing is already implemented in the RX portion of the monostatic radar implementation, gr-radar-mono.) _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
