Attached is a simple testbench.

Here is what I have in my directory and how I run:

$ ls *.v
phase_acc.v  phase_acc_tb.v  setting_reg.v


$ iverilog *.v ; ./a.out > output ; cat output
    123456
2952913472
1610736192
 268558912
3221348928
1879171648
 536994368
3489784384
2147607104
 805429824
3758219840
2416042560
1073865280
4026655296
2684478016
1342300736
    123456
End of simulation

Brian

Attachment: phase_acc_tb.v
Description: unknown/unknown

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