Brian Thanks again for the testbed file. I see what phase_acc does now. When we do a downconversion, the initial phase that gets written to the FR_RX_PHASE_0 register is 0, right? I just want to make sure of that and that the phase value repeats after about 16 clock cycles. I would just like to know if you know of a good testbed tutorial around. What I would like to do now is generate a sine wave at 20MHz, sampled at 64MHz and save this to a text file. I would also like to save the phase values generated by phase_acc to a text file. I then want to write a testbench for cordic.v with the incoming sine wave and phase values and save the output from the cordic to a text or datafile. If you know how to access and read/write files in Iverilog, could you please just show me a line of code or two to do it?
Thank you very much. Sebastiaan Heunis _______________________________________________ Discuss-gnuradio mailing list [email protected] http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
