At high SNR, a single bit is probably enough in the detector and 15 bits in the phase accumulator is also likely more than enough. The error, in my opinion, is elsewhere.
Tell us about your work here please: https://www.cgran.org/ after you have set up your git repository here: https://github.com/ and here are some useful instructions http://gnuradio.org/redmine/projects/gnuradio/wiki/DevelopingWithGit Thanks, in advance, for sharing Bob On Thu, Dec 15, 2011 at 1:52 AM, Phone Naing MYINT < phonenaing.my...@sg.panasonic.com> wrote: > Hi,**** > > ** ** > > Anyone here implemented freq/phase correction and symbol timing correction > in USRP’s FPGA? **** > > ** ** > > Recently I implemented Costas loop and Muller & Mueller algorithm in RTL > by referring the gnuradio code. Now I’m testing it on FPGA. I can get > correct demodulated data(DQPSK) at initial few thousand symbols. After that > I’m getting all rubbish data. **** > > ** ** > > I think the problem with my RTL implementation is not good enough > bit-resolution (unlike implementation on PC). Currently I’m using 15-bits > resolution for decimal part. Anyone has any suggestion ?**** > > ** ** > > PN **** > > _______________________________________________ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > https://lists.gnu.org/mailman/listinfo/discuss-gnuradio > > -- Bob McGwier Facebook: N4HYBob ARS: N4HY
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