Hello Daniele, I've included the USRP users mailing list [1], since this is not related to GNU Radio but to the USRP.
The N210 has a fixed master clock rate of 100MHz, generated from the 10MHz reference by using PLL controlled clock multipliers. The ADC always samples at 100MHz complex, then passes this 100MS/s signal to the FPGA, which then shifts it (if you use an RF frequency that cannot be synthesized by the daughterboard in use exactly) digitally by multiplying it with a complex sine, lowpasses it to fulfill nyquist for your desired sampling rate, and then decimates it. The sample stream at your desired rate is then passed on via gigabit ethernet. First of all, let's get a relative error estimate: 9.32e-3/10e6 is about 1ppb error, which is fantastically low from my point of view; this might as well be caused by numerical accuracy in the FPGA, e.g. when shifting the signal or decimating it; this is all fixed point arithmetic! Then, your 200kHz sampling rate is an odd fraction of 100MHz; try 250kHz, to get nicer low pass filtering (I always thought 250kHz was the minimum usable sampling rate). Also, how long did you observe your phase drift? To estimate a relative error of 1e-9 reliably, you'll need a lot of samples (remember: you always have quantization noise in digital systems, so even given perfect analog signals and analog components at 0K temperature, you don't get infinite SNR). Hope that was a little helpful! Greetings, Marcus Müller [1] subscribe via http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com On 17.06.2014 21:37, Daniele Nicolodi wrote: > Hello, > > I'm using an Ettus Research N210 with a LFRX daughter-board to do data > measure the phase of a signals referred to a 10 MHz clock. > > To start I want to characterize the phase noise of the device, therefore > I send to both the RX channel and to the frequency reference input the > same 10 MHz signal. I configured the N210 for 200 kHz sampling and a > carrier frequency of 10 MHz. > > When I look at the data I obtain, I see a constant phase drift > corresponding to a 9.32 mHz frequency different between the signal I > send to the RX channel and the frequency at which the N210 does the > demodulation. > > Given that the signal and the clock are derived from the same oscillator > (in this simple case are the exact same signal), where does this > difference come from? How can I get rid of it? > > I imagine it comes from the fact that the ADC sampling frequency is not > an exact multiple of the signal frequency, but I haven't found details > on how the ADC sampling frequency is generated, thus I have no idea > about how to make it an exact multiple of the signal frequency. > > Thanks. Cheers, > Daniele > > _______________________________________________ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > https://lists.gnu.org/mailman/listinfo/discuss-gnuradio _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org https://lists.gnu.org/mailman/listinfo/discuss-gnuradio
