I suppose you'd have to modify the FPGA-to-ADC interface to bring in fewer bits from the ADC. I don't think there's a way to lower ADC resolution at the ADC itself.
on Jun 30, 2014, Leonardo S. Cardoso <[email protected]> wrote:
Hello everyone,I excuse myself on advance by my noob question...I have an N210 with an SBX front end, and I want to experiment with decoding signals at a lower resolution, rather than the default 12 bits provided by the N210 ADCs. Does anyone know if (and how) can I limit the resolution of the ADCs arbitrarily?I am aware that I can reduce the resolution afterwards, mapping the signals to a lower resolution in base band, but I'd really like to do that before the DDC at the FPGA.Cheers to everyone!
Leonardo S. Cardoso
_______________________________________________
Discuss-gnuradio mailing list
[email protected]
https://lists.gnu.org/mailman/listinfo/discuss-gnuradio
_______________________________________________ Discuss-gnuradio mailing list [email protected] https://lists.gnu.org/mailman/listinfo/discuss-gnuradio
