Yes, 14 bits... mistyped the ADC resolution...

Thanks, Matt. I'll investigate this idea...

Leonardo S. Cardoso
[email protected]


On Mon, Jun 30, 2014 at 4:46 PM, Matt Ettus <[email protected]> wrote:

> The n200 and n210 have 14 bit ADCs.
>
> In any case, you can fake fewer bits by zeroing the low order bits in the
> fpga.
>
> Matt
> On Jun 30, 2014 10:38 AM, "Leonardo S. Cardoso" <[email protected]> wrote:
>
>> Hello everyone,
>>
>> I excuse myself on advance by my noob question...
>>
>> I have an N210 with an SBX front end, and I want to experiment with
>> decoding signals at a lower resolution, rather than the default 12 bits
>> provided by the N210 ADCs. Does anyone know if (and how) can I limit the
>> resolution of the ADCs arbitrarily?
>>
>> I am aware that I can reduce the resolution afterwards, mapping the
>> signals to a lower resolution in base band, but I'd really like to do that
>> before the DDC at the FPGA.
>>
>> Cheers to everyone!
>>
>> Leonardo S. Cardoso
>> [email protected]
>>
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>>
>>
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