Hi Maurizio, > And what about the new RFNoC and GRC to be run on an E310? these are two different aspects: GRC is a flowgraph /design/ tool. You wouldn't run it on the E310 (especially as it is a graphical tool). It can generate headless flow graphs set up by python programs that you can copy over to the E310 -- that's the usage of GRC I'd recommend in this case.
You can use gr-ettus to design flow graphs even if the PC you use for design doesn't have access to a USRP at all -- the USRP/RFNoC is needed at run time only. > The only way out I can think of is to > rely on data saved to file to be analysed in a post-processing step. To be honest, yes, that is the problem with embedded devices. They are limited in the ways you can interact with them and with the computation happening on them. A very software design driven approach would be to design good unit tests, that you would first verify with simulated signals on your host computer, and use them to understand the workings of your USRP. If you limit yourself to low rates (go for < 1MS/s for a start), you might also be able to build a flow graph that uses e.g. a ZMQ sink to send the processed data to your host PC, where another flow graph takes care of visualization. Greetings, Marcus On 09.09.2015 11:30, Maurizio Crozzoli wrote: > And what about the new RFNoC and GRC to be run on an E310? > > From Ettus site we are told that "RFNoC has been integrated into UHD for our > third generation USRP SDRs (X300-series, E300-series, and future devices)". > Furthermore Ettus site shows some examples where RFNoC blocks are used under > GRC, which is a GUI environment (but they are run on an X series HW...). > > So the new question is: what is the right methodology to make designs under > GRC to be run under an E310? What about initial testing steps (especially if > you want to use RFNoc)? > > About RFNoC I could imagine a step-wise approache where I prepare the Python > with GRC (where the RFNoC OOT modules are installed) and then I run it on > the E310 (where the RFNoC non-default FPGA configuration is installed). But > what about testing such design? "If your flow graph doesn't use graphical > sinks" how can you test your design? The only way out I can think of is to > rely on data saved to file to be analysed in a post-processing step. > > Needless to say that comments are welcome... > > TIA! > > BR, > Maurizio. > > > > -- > View this message in context: > http://gnuradio.4.n7.nabble.com/On-the-right-approach-for-developing-applications-to-be-run-on-an-E310-tp55779p55905.html > Sent from the GnuRadio mailing list archive at Nabble.com. > > _______________________________________________ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > https://lists.gnu.org/mailman/listinfo/discuss-gnuradio
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