Hello Vikesh, Please take a look at this section of our "Getting started with RFNoC Development" guide, specifically the "wiring CE" section [1]. As Marcus stated, NoC blocks start with "noc_block_", and this is the way to identify them in the sources.
On 12/06/2016 10:37 PM, Vishwesh Rege wrote: >>>>What are the list of blocks that I can add? In that page that I just referenced there is a list of the current noc_blocks provided by Ettus. >>>>But what functionality do the other FIFOs provide (when am I supposed to use them)? >>>>chdr_fifo_large >>>>noc_block_axi_dma_fifo >>>>split_stream_fifo >>>>ram_to_fifo ... etc. Talking about "blocks' in a really general way, you'd only have to take in consideration the 'noc_block_axi_dma_fifo". The others that you listed are part of the library because the serve other functions at a lower level of abstraction to generate the blocks that you are going to use directly in your application. >>>>Using the make.py approach: >>>>From what I understand make.py only generates an output.v file right? After running make.py do I have to copy the contents of the output.v file to >>>>rfnoc_ce_auto_inst_x310.v? No. make.py will take the blocks that you provided as parameters, and with that it will generate your rfnoc_ce_auto_inst file and right after will kick your bitstream build. The script only needs you to have vivado installed, but you don't have to copy contents of files. It appears that you gave the script the "-o output.v" option. This will generate a file without kicking the build, but this option you'd use as a verification of the file correctness. If you just skip this option, the rfnoc_ce_auto_inst_x310.v file will be overwritten directly and your build will start automatically. >>>>From these I could add noc_block_digital_gain (built successfully) >>>>but couldn't add chdr_fifo_large (running make X310_RFNOC_HLS_HG gave an error) Could you please tell us what error did it throw? >>>>Finally what difference does it make if I run "make X310_RFNOC_HG" versus "make X310_RFNOC_HLS_HG" The X310_RFNOC_HLS_HG target uses "High Level Synthesis" to generate the build. This is a way of generating hardware designs by the means of software algorithms (i.e. you use C, C++ or SystemC to describe your hardware, and the build system will translate that into hardware). By selecting this target you are telling the build system that you wrote some C/C++/SystemC code, located it at usrp3/lib/hls, and you want it to be part of your design. In that directory there is an 'addsub' block written in HLS as an example. The X310_RFNOC_HG will synthesize your design using verilog sources. Cheers, - Nicolas [1] https://kb.ettus.com/Getting_Started_with_RFNoC_Development#Wiring_up_computation_engines_and_building_the_FPGA_image On Tue, Dec 6, 2016 at 10:45 PM, Marcus Müller <[email protected]> wrote: > A NoC block should, as far as I can tell, always start with noc_block_. > > > Best regards, > > Marcus > > On 12/06/2016 10:37 PM, Vishwesh Rege wrote: > > Hi, > > What are the list of blocks that I can add? > > For example, > Looking at the list of blocks in usrp3_rfnoc/lib/rfnoc/Makefile.srcs > > From these I could add noc_block_digital_gain (built successfully) > but couldn't add chdr_fifo_large (running make X310_RFNOC_HLS_HG gave an > error) > > How do I know which blocks will work? > > For the error I'm getting in GRC "FIFO_0 block missing" I think > noc_block_axi_fifo_loopback is probably the right one > But what functionality do the other FIFOs provide (when am I supposed to > use them)? > chdr_fifo_large > noc_block_axi_dma_fifo > split_stream_fifo > ram_to_fifo ... etc. > > Thanks, > Vishwesh > > -- > To change the blocks, you need to edit rfnoc_ce_auto_inst_x310.v twice: > You need to change NUM_CE (at the top), and then the actual block list. > > For FIFOs, you can go to the bottom and use the generate for loop to add > more FIFOs. > > You can use make.py to autogenerate this file (in > usrp3/tools/scripts/make.py). > > Cheers, > Martin > > On 12/04/2016 05:55 PM, Vishwesh Rege wrote: > > Hi, > > > > I want to add the FIFO block in usrp3_rfnoc/lib/fifo to USRP along with > > the addsub module in usrp3_rfnoc/lib/hls folder. > > > > I'm running make X310_RFNOC_HLS_HG from usrp3_rfnoc/top/x300 directory > > and then flashing the generated image in build/. > > > > However, the FIFO isn't included in the image for some reason. Only the > > following RFNoC blocks are actually flashed: > > | | | * DmaFIFO_0 > > | | | * Radio_0 > > | | | * Radio_1 > > | | | * AddSub_0 > > | | | * FIR_0 > > | | | * FFT_0 > > | | | * Window_0 > > | | | * NullSrcSink_0 > > | | | * SigGen_0 > > | | | * MovingAverage_0 > > | | | * VectorIIR_0 > > | | | * KeepOneInN_0 > > | | | * fosphor_0 > > > > The Makefile usrp3_rfnoc/top/x300/Makefile.x300.inc already includes > > FIFO_SRCS in DESIGN_SRCS > > > > Do I need to make any changes to include the FIFO? > > > > Any help is appreciated. > > > > > > > > > > > _______________________________________________ > Discuss-gnuradio mailing > [email protected]https://lists.gnu.org/mailman/listinfo/discuss-gnuradio > > > > _______________________________________________ > Discuss-gnuradio mailing list > [email protected] > https://lists.gnu.org/mailman/listinfo/discuss-gnuradio > >
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