Sounds like a fun study. I looked at using some of those ADRF6510 ADC
drivers with built-in programmable analog LPFs a while back. They're
highly integrated but fairly expensive and really power-hungry.
Eric
On 05/21/2018 11:21 AM, Marcus D. Leech wrote:
On 05/21/2018 01:59 PM, Dan CaJacob wrote:
Hey Marcus,
This may not be what you are looking for, but these are awesome. They
may be going to space soon :)
http://www.newedges2.com/products/SAX239-R2_Datasheet_February-27th-2018.pdf
Interesting. Not quite what I was looking for.
Basically just doing a design-tradeoff study for grins.
Fixed sample rate and filter/decimate in a "sized-for-economy" FPGA, or
variable sample-rate, and a chain of tuneable analog filters in front of the
ADC.
A chain of 3 or 4 2nd-order active-lowpass filters using video op-amps
would probably work OK. Use digipots to set the R values, and use a fixed
value for C, or perhaps selectable C as well (probably only two or
three values).
Or, a small number (4?) of selectable L-C-R low-pass filters, and fix
the sample rates to a small number.
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