T wrote:
Especially since they use two different vertical settings for the 'good' and 'bad' signals!
That's not the worst part. I can read a scope display for myself and see that the settings were changed.
The big flaw with this particular measurement (other than the horizontal sweep has been blown up to greatly exaggerate the "problem")
What makes you think that?
is that it shows the jitter at the end of an S/P-DIF link before it has been processed by the receiver chip.The receiver tracks and reconstructs the incoming clock with a phase locked loop that substantially reduces the jitter (noise).
Reducing noise on narrowband signals like clocks and carriers is exactly what phase lock loops *do*; they behave like tunable, very narrowband, high-Q filters that automatically track the signal's frequency.
Yes, but the AESSBU/SPDIF standard is such that even the best PLL can't do this perfectly.
Sure, it's possible to be sloppy in the design of a PLL. But if you are, chances are it wouldn't work at all. And if it does work, it probably works well.
...possible...chances are...probably...
Again, before any of this is even relevant, one must conduct the properly controlled studies to determine whether clock jitter is even a real, audible problem. I see no evidence that it is.
Triode posted a link to a paper published by the AES that discussed the problem of jitter concludes:
"It can be shown that, compared to low oversampling multi-bit designs, pulse density modulation converters are much more sensitive to jitter when producing low frequency audio signals. This phenomena may explain certain subjective characteristics of PDM DACs which cannot otherwise be rationalised. A simple model of jitter error audibility has shown that
white jitter noise of up to 180 ps can be tolerated in a DAC, but that even lower levels of sinusoidal jitter may be audible."
The ironic thing about this discussion is that the Squeezebox is not s S/P-DIF receiver that has to track an external clock. The Squeezebox requests TCP/IP packets containing audio data, and it plays them at its own pace using its own internal crystal oscillator. While I do not have a schematic of a Squeezebox, I think it quite likely that this same (or another) crystal oscillator also clocks the DACs providing analog audio to the jacks. So there's no S/P-DIF link and no PLL reconstructing clock anywhere in the Squeezebox's audio path. But if you connect an external DAC, perhaps with one of those $500 jitter removers, now you have introduced one or even two "flawed" S/P-DIF links and clock recovery circuits, each adding their own jitter!
The discussion was originally about the possibility for improving the performance of the SB by adding a more accurate clock/crystal oscillator. As you rightly say, with no external DAC there is no SPDIF link but there is still the possiblity that the internal clock can be improved upon.
So it seems to me that if you're really worried about jitter, just use the analog outputs on the Squeezebox and don't even connect anything to the S/P-DIF outputs!
That is of course not feasible if you want to use an external DAC, in which case you need to minimise jitter, which brings back to where we started.
R. -- http://robinbowes.com
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