David Kuehling wrote: > But doesn't reading from the APB synchronize the CPU to the APB clock > (i.e. execution of the read finishes always after the same constant time > relative to a APB clock edge)?
That's the strange thing - it doesn't seem to work like this. Otherwise, I think I should have gotten perfect synchronization already before. The delay for writing to GPIO registers, which are also on APB, is in the order of 8 PCLK cycles, so those bus cycles seem to be complicated. Wish we could just peek at the sources to see what's really going on inside ;-) - Werner _______________________________________________ Qi Hardware Discussion List Mail to list (members only): [email protected] Subscribe or Unsubscribe: http://lists.en.qi-hardware.com/mailman/listinfo/discussion
