Anyone have any experience with a 4-port switch using the Intel
82559ER chipset? I've got 1.2-BETA-1-embedded up and running on a
piece of hardware with one of these embedded on the motherboard, and
it sees the entire switch as a single interface (fxp0, in this case).
Related dmesg follows:
fxp0: <Intel 82559ER Embedded 10/100 Ethernet> port 0xee00-0xee3f mem
0xc0100000-0xc0100fff,0xc0120000-0xc013ffff irq 9 at device 0.0 on
pci1
miibus0: <MII bus> on fxp0
fxp0: Ethernet address: xx:xx:xx:fe:09:98
fxp0: link state changed to UP
fxp0: device timeout
It's also noteworthy that to get this and it's sister single-port
(fxp1, dmesg below) to work, I have to disable tcp-offload. During
boot, fxp1 comes up with ffff.ffff.ffff as it's MAC, but then shows up
as 02:ea:fa:34:36:2e
fxp1: <Intel 82559ER Embedded 10/100 Ethernet> port 0xea00-0xea3f mem
0xc0140000-0xc0140fff,0xc0160000-0xc017ffff irq 12 at device 1.0 on
pci1
fxp1: Disabling dynamic standby mode in EEPROM
fxp1: New EEPROM ID: 0xfffd
fxp1: EEPROM checksum @ 0xff: 0xffff -> 0xbbb9
miibus1: <MII bus> on fxp1
fxp1: Ethernet address: ff:ff:ff:ff:ff:ff
fxp1: link state changed to UP
I'm mostly interested in controlling the individual ports, but don't
know how possible that is. As things stand, devices on separate ports
are capable of communicating with each other, but the traffic is
unseen on fxp0. Any priors?
<ascii>
fxp0 fxp1
| |
____________|____________ |
| | | | |
PHY PHY PHY PHY PHY
</ascii>
RB
