Right, that's why it is incorrect to refer to it as "standard" behavior.
Behaviors I've seen include various combinations of:
1. disallowing enregistering
2. preventing folding multiple loads/stores together
3. preventing reordering across expressions with volatiles
4. inserting memory load/store fences
1 && 2 for memory-mapped IO and 3 && 4 for concurrent access to shared
memory.
D volatile isn't implemented, either.
At least for dmd it disables instruction rescheduling.
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