We don't need 4 for concurrent access. That can be done in asm. What we need is a way to apply the same constraints on the compiler that asm already allows us to apply to the hardware, which is 1-3.
On Jul 25, 2012, at 9:37 PM, "Martin Nowak" <[email protected]> wrote: >> Right, that's why it is incorrect to refer to it as "standard" behavior. >> Behaviors I've seen include various combinations of: >> >> 1. disallowing enregistering >> 2. preventing folding multiple loads/stores together >> 3. preventing reordering across expressions with volatiles >> 4. inserting memory load/store fences >> > 1 && 2 for memory-mapped IO and 3 && 4 for concurrent access to shared memory. > >> >> D volatile isn't implemented, either. >> > At least for dmd it disables instruction rescheduling. > _______________________________________________ > dmd-internals mailing list > [email protected] > http://lists.puremagic.com/mailman/listinfo/dmd-internals _______________________________________________ dmd-internals mailing list [email protected] http://lists.puremagic.com/mailman/listinfo/dmd-internals
