On 07.09.2017 16:12, Erik Christiansen wrote:
If the firewall is on a FPGA, then we know what every gate is doing, as we have the VHDL source for it.
An purely FPGA-based firewall (w/o an cpu in it), specifically synthesized for a given ruleset seems an very interesting approach. Anyone here w/ some practical vhdl experience ? --mtx _______________________________________________ Dng mailing list [email protected] https://mailinglists.dyne.org/cgi-bin/mailman/listinfo/dng
