Hi
Is it possible to configure the \vdhlflow command to only include
conditional statements and associated comments
instead of all the code as well.
For the simple example below, the reset case includes the following two
lines in the diagram
s_t_MpxState <= t_MpxIdle;
v_DataTransaction := '1';
This sometimes clutters the diagram especially when there are many such
statements.
Is it possible to replace the code with just the comment ?
Can the same be done for the case statement ?
Thanx for your help
Vicki
-----------------------------------------------------------------------------
--! @brief Process to demonstrate vhdlflow
--!
--! Check if only conditional statements with comment can be included in
--! graph.
--!
--! @param[in] p_Clk System bus clock
--!
--! @vhdlflow TestFlow
-----------------------------------------------------------------------------
PROC_TEST_FLOW : process (p_Clk)
begin
if (reset = '1') then
--! Reset all signals and variables to safe condition
s_t_MpxState <= t_MpxIdle;
v_DataTransaction := '1';
elsif (p_Clk'event and p_Clk = '1') then
case s_t_MpxState is
-----------------------------------------------------------------------
when t_MpxIdle1 => --! S1
s_t_MpxState <= t_MpxIdle2;
-----------------------------------------------------------------------
when t_MpxIdle2 => --! S2
s_t_MpxState <= t_MpxIdle1;
-----------------------------------------------------------------------
when others => s_t_MpxState <= t_MpxIdle1;
end case;
end if;
end process PROC_TEST_FLOW;
------------------------------------------------------------------------------
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