tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head: c749b504bf85eee2edc857c4549d83d34730113c
commit: 8d47a4e3262de5f749806245d087dc8aa5ae2253 [852/868] drm/dsc: Update
drm_dsc to reflect native 4.2.0 DSC spec
config: riscv-defconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 7.4.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 8d47a4e3262de5f749806245d087dc8aa5ae2253
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <l...@intel.com>
All warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/drm_dsc.c:9:0:
drivers/gpu/drm/drm_dsc.c: In function 'drm_dsc_compute_rc_parameters':
include/linux/kernel.h:821:29: warning: comparison of distinct pointer types
lacks a cast
(!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
^
include/linux/kernel.h:835:4: note: in expansion of macro '__typecheck'
(__typecheck(x, y) && __no_side_effects(x, y))
^~~~~~~~~~~
include/linux/kernel.h:845:24: note: in expansion of macro '__safe_cmp'
__builtin_choose_expr(__safe_cmp(x, y), \
^~~~~~~~~~
include/linux/kernel.h:861:19: note: in expansion of macro '__careful_cmp'
#define max(x, y) __careful_cmp(x, y, >)
^~~~~~~~~~~~~
>> drivers/gpu/drm/drm_dsc.c:435:16: note: in expansion of macro 'max'
max_offset = max(max_offset,
^~~
include/linux/kernel.h:821:29: warning: comparison of distinct pointer types
lacks a cast
(!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
^
include/linux/kernel.h:835:4: note: in expansion of macro '__typecheck'
(__typecheck(x, y) && __no_side_effects(x, y))
^~~~~~~~~~~
include/linux/kernel.h:845:24: note: in expansion of macro '__safe_cmp'
__builtin_choose_expr(__safe_cmp(x, y), \
^~~~~~~~~~
include/linux/kernel.h:861:19: note: in expansion of macro '__careful_cmp'
#define max(x, y) __careful_cmp(x, y, >)
^~~~~~~~~~~~~
drivers/gpu/drm/drm_dsc.c:440:16: note: in expansion of macro 'max'
max_offset = max(max_offset,
^~~
vim +/max +435 drivers/gpu/drm/drm_dsc.c
279
280 /**
281 * drm_dsc_compute_rc_parameters() - Write rate control
282 * parameters to the dsc configuration defined in
283 * &struct drm_dsc_config in accordance with the DSC 1.2
284 * specification. Some configuration fields must be present
285 * beforehand.
286 *
287 * @vdsc_cfg:
288 * DSC Configuration data partially filled by driver
289 */
290 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
291 {
292 unsigned long groups_per_line = 0;
293 unsigned long groups_total = 0;
294 unsigned long num_extra_mux_bits = 0;
295 unsigned long slice_bits = 0;
296 unsigned long hrd_delay = 0;
297 unsigned long final_scale = 0;
298 unsigned long rbs_min = 0;
299 unsigned long max_offset = 0;
300
301 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
302 /* Number of groups used to code each line of a slice */
303 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width /
2,
304 DSC_RC_PIXELS_PER_GROUP);
305
306 /* chunksize in Bytes */
307 vdsc_cfg->slice_chunk_size =
DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
308
vdsc_cfg->bits_per_pixel,
309 (8 * 16));
310 } else {
311 /* Number of groups used to code each line of a slice */
312 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
313 DSC_RC_PIXELS_PER_GROUP);
314
315 /* chunksize in Bytes */
316 vdsc_cfg->slice_chunk_size =
DIV_ROUND_UP(vdsc_cfg->slice_width *
317
vdsc_cfg->bits_per_pixel,
318 (8 * 16));
319 }
320
321 if (vdsc_cfg->convert_rgb)
322 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
323 (4 *
vdsc_cfg->bits_per_component + 4)
324 - 2);
325 else if (vdsc_cfg->native_422)
326 num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
327 (4 * vdsc_cfg->bits_per_component + 4) +
328 3 * (4 * vdsc_cfg->bits_per_component) - 2;
329 else
330 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
331 (4 * vdsc_cfg->bits_per_component + 4) +
332 2 * (4 * vdsc_cfg->bits_per_component) - 2;
333 /* Number of bits in one Slice */
334 slice_bits = 8 * vdsc_cfg->slice_chunk_size *
vdsc_cfg->slice_height;
335
336 while ((num_extra_mux_bits > 0) &&
337 ((slice_bits - num_extra_mux_bits) %
vdsc_cfg->mux_word_size))
338 num_extra_mux_bits--;
339
340 if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
341 vdsc_cfg->initial_scale_value = groups_per_line + 8;
342
343 /* scale_decrement_interval calculation according to DSC spec
1.11 */
344 if (vdsc_cfg->initial_scale_value > 8)
345 vdsc_cfg->scale_decrement_interval = groups_per_line /
346 (vdsc_cfg->initial_scale_value - 8);
347 else
348 vdsc_cfg->scale_decrement_interval =
DSC_SCALE_DECREMENT_INTERVAL_MAX;
349
350 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
351 (vdsc_cfg->initial_xmit_delay *
352 vdsc_cfg->bits_per_pixel + 8) / 16 +
num_extra_mux_bits;
353
354 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
355 DRM_DEBUG_KMS("FinalOfs < RcModelSze for this
InitialXmitDelay\n");
356 return -ERANGE;
357 }
358
359 final_scale = (vdsc_cfg->rc_model_size * 8) /
360 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
361 if (vdsc_cfg->slice_height > 1)
362 /*
363 * NflBpgOffset is 16 bit value with 11 fractional bits
364 * hence we multiply by 2^11 for preserving the
365 * fractional part
366 */
367 vdsc_cfg->nfl_bpg_offset =
DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
368
(vdsc_cfg->slice_height - 1));
369 else
370 vdsc_cfg->nfl_bpg_offset = 0;
371
372 /* 2^16 - 1 */
373 if (vdsc_cfg->nfl_bpg_offset > 65535) {
374 DRM_DEBUG_KMS("NflBpgOffset is too large for this slice
height\n");
375 return -ERANGE;
376 }
377
378 if (vdsc_cfg->slice_height > 2)
379 vdsc_cfg->nsl_bpg_offset =
DIV_ROUND_UP((vdsc_cfg->second_line_bpg_offset << 11),
380
(vdsc_cfg->slice_height - 1));
381 else
382 vdsc_cfg->nsl_bpg_offset = 0;
383
384 if (vdsc_cfg->nsl_bpg_offset > 65535) {
385 DRM_DEBUG_KMS("NslBpgOffset is too large for this slice
height\n");
386 return -ERANGE;
387 }
388
389 /* Number of groups used to code the entire slice */
390 groups_total = groups_per_line * vdsc_cfg->slice_height;
391
392 /* slice_bpg_offset is 16 bit value with 11 fractional bits */
393 vdsc_cfg->slice_bpg_offset =
DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
394
vdsc_cfg->initial_offset +
395 num_extra_mux_bits)
<< 11),
396 groups_total);
397
398 if (final_scale > 9) {
399 /*
400 * ScaleIncrementInterval =
401 * finaloffset/((NflBpgOffset +
SliceBpgOffset)*8(finalscale - 1.125))
402 * as (NflBpgOffset + SliceBpgOffset) has 11 bit
fractional value,
403 * we need divide by 2^11 from pstDscCfg values
404 */
405 vdsc_cfg->scale_increment_interval =
406 (vdsc_cfg->final_offset * (1 << 11)) /
407 ((vdsc_cfg->nfl_bpg_offset +
408 vdsc_cfg->nsl_bpg_offset +
409 vdsc_cfg->slice_bpg_offset) *
410 (final_scale - 9));
411 } else {
412 /*
413 * If finalScaleValue is less than or equal to 9, a
value of 0 should
414 * be used to disable the scale increment at the end of
the slice
415 */
416 vdsc_cfg->scale_increment_interval = 0;
417 }
418
419 if (vdsc_cfg->scale_increment_interval > 65535) {
420 DRM_DEBUG_KMS("ScaleIncrementInterval is large for
slice height\n");
421 return -ERANGE;
422 }
423
424 /*
425 * DSC spec mentions that bits_per_pixel specifies the target
426 * bits/pixel (bpp) rate that is used by the encoder,
427 * in steps of 1/16 of a bit per pixel
428 */
429 if (vdsc_cfg->dsc_version_minor == 2 && (vdsc_cfg->native_420
|| vdsc_cfg->native_422)) {
430
431 max_offset = compute_offset(vdsc_cfg,
DSC_RC_PIXELS_PER_GROUP, groups_per_line,
432
DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay,
433
DSC_RC_PIXELS_PER_GROUP));
434
> 435 max_offset = max(max_offset,
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org Intel Corporation
.config.gz
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