There is a possibility of a race condition between interrupt subroutine
which accesses the interrupt related registers to clear the statuses before
handling the interrupt and other functions such as display soft reset,
runtime resume/suspend etc which also access the interrupt related
registers.  To prevent such scenarioes, use a spinlock to serialize access
to interrupt related registers.

Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display 
SubSystem")
Signed-off-by: Devarsh Thakkar <[email protected]>
---
 drivers/gpu/drm/tidss/tidss_dispc.c | 4 ++++
 drivers/gpu/drm/tidss/tidss_irq.c   | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c 
b/drivers/gpu/drm/tidss/tidss_dispc.c
index b04419b24863..cec59deff015 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -2767,8 +2767,12 @@ static void dispc_init_errata(struct dispc_device *dispc)
  */
 static void dispc_softreset_k2g(struct dispc_device *dispc)
 {
+       unsigned long flags;
+
+       spin_lock_irqsave(&dispc->tidss->wait_lock, flags);
        dispc_set_irqenable(dispc, 0);
        dispc_read_and_clear_irqstatus(dispc);
+       spin_unlock_irqrestore(&dispc->tidss->wait_lock, flags);
 
        for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx)
                VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0);
diff --git a/drivers/gpu/drm/tidss/tidss_irq.c 
b/drivers/gpu/drm/tidss/tidss_irq.c
index 604334ef526a..d053dbb9d28c 100644
--- a/drivers/gpu/drm/tidss/tidss_irq.c
+++ b/drivers/gpu/drm/tidss/tidss_irq.c
@@ -60,7 +60,9 @@ static irqreturn_t tidss_irq_handler(int irq, void *arg)
        unsigned int id;
        dispc_irq_t irqstatus;
 
+       spin_lock(&tidss->wait_lock);
        irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc);
+       spin_unlock(&tidss->wait_lock);
 
        for (id = 0; id < tidss->num_crtcs; id++) {
                struct drm_crtc *crtc = tidss->crtcs[id];
-- 
2.39.1

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