[PATCH RFT 07/14] drm/msm/a6xx: Resolve the meaning of UBWC_MODE

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>

This bit is set iff the UBWC version is 1.0. That notably does not
include QCM2290's "no UBWC".

Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 
e1eab0906b6c460528da82a94a285ef181e0b479..d47726ea8818a9660eadd52d97dde1489a884684
 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -663,10 +663,10 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
        u8 uavflagprd_inv = adreno_is_a650_family(adreno_gpu) || 
adreno_is_a7xx(adreno_gpu) ? 2 : 0;
        const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->common_ubwc_cfg;
        u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit;
+       bool ubwc_mode = cfg->ubwc_enc_version == UBWC_1_0;
        bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
        u32 hbb_hi = hbb >> 2;
        u32 hbb_lo = hbb & 3;
-       u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
        u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);
 
        gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,

-- 
2.49.0