From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
Make use of the SSOT config database, this time including the HBB
which doesn't seem to change between configurations.
Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index
1344d461c16dfa942b0b65d747eadca507116806..691393e958cf164b69e7fe1a9df313f813473a35
100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1753,6 +1753,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct qcom_ubwc_cfg_data *common_cfg;
struct a5xx_gpu *a5xx_gpu = NULL;
struct adreno_gpu *adreno_gpu;
struct msm_gpu *gpu;
@@ -1789,15 +1790,12 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
/* Set up the preemption specific bits and pieces for each ringbuffer */
a5xx_preempt_init(gpu);
- /* Set the highest bank bit */
- if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu))
- adreno_gpu->ubwc_config->highest_bank_bit = 2;
- else
- adreno_gpu->ubwc_config->highest_bank_bit = 1;
+ /* Inherit the common config and make some necessary fixups */
+ common_cfg = qcom_ubwc_config_get_data();
+ if (IS_ERR(common_cfg))
+ return ERR_PTR(-EINVAL);
- /* a5xx only supports UBWC 1.0, these are not configurable */
- adreno_gpu->ubwc_config->macrotile_mode = 0;
- adreno_gpu->ubwc_config->ubwc_swizzle = 0x7;
+ *adreno_gpu->ubwc_config = *common_cfg;
adreno_gpu->uche_trap_base = 0x0001ffffffff0000ull;
--
2.49.0
