Re: [PATCH v9 09/14] drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer

Thu, 08 May 2025 13:43:11 -0700 



On 5/6/2025 8:47 AM, Jun Nie wrote:

The stage contains configuration for a mixer pair. Currently the plane
supports just one stage and 2 pipes. Quad-pipe support will require
handling 2 stages and 4 pipes at the same time. In preparation for that
add a separate define, PIPES_PER_PLANE, to denote number of pipes that
can be used by the plane.

Signed-off-by: Jun Nie <jun....@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>


Hi Jun,


I think the comment from v7 about propogating the PIPES_PER_PLANE change 
to _dpu_plane_color_fill() got dropped in this version [1].



Also, any reason PIPES_PER_STAGE was kept for 
dpu_plane_danger_signal_ctrl()?


Thanks,

Jessica Zhang


[1] 
https://patchwork.freedesktop.org/patch/640534/?series=139762&rev=6#comment_1171802



---
  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c    |  4 ++--
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h |  1 +
  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 14 +++++++-------
  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h   |  4 ++--
  4 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 
6338603bf8be9fcc4324b098d5d69d20235cdbae..d710b4eec7ad946a4cf74d6ac5f4db90e8dcf1fd
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -463,7 +463,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc 
*crtc,
                if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
                        bg_alpha_enable = true;

  
-		for (i = 0; i < PIPES_PER_STAGE; i++) {

+               for (i = 0; i < PIPES_PER_PLANE; i++) {
                        if (!pstate->pipe[i].sspp)
                                continue;
                        set_bit(pstate->pipe[i].sspp->idx, fetch_active);
@@ -1272,7 +1272,7 @@ static int dpu_crtc_reassign_planes(struct drm_crtc 
*crtc, struct drm_crtc_state
        return ret;
  }

  
-#define MAX_CHANNELS_PER_CRTC 2

+#define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE
  #define MAX_HDISPLAY_SPLIT 1080

  
  static struct msm_display_topology dpu_crtc_get_topology(

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 
8d820cd1b5545d247515763039b341184e814e32..b0ed41108a32158c0bc3be2e25fc229b218fd6c5
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -34,6 +34,7 @@
  #define DPU_MAX_PLANES                        4
  #endif

  
+#define PIPES_PER_PLANE			2

  #define PIPES_PER_STAGE                       2
  #ifndef DPU_MAX_DE_CURVES
  #define DPU_MAX_DE_CURVES             3
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 
4cb81a6a692be51d342d9a6f322b632e5fd07b2c..ea7e3fdf52f726737941ad33218a843dca17280b
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1078,7 +1078,7 @@ static int dpu_plane_virtual_atomic_check(struct 
drm_plane *plane,
                 * resources are freed by dpu_crtc_assign_plane_resources(),
                 * but clean them here.
                 */
-               for (i = 0; i < PIPES_PER_STAGE; i++)
+               for (i = 0; i < PIPES_PER_PLANE; i++)
                        pstate->pipe[i].sspp = NULL;

  
  		return 0;

@@ -1129,7 +1129,7 @@ static int dpu_plane_virtual_assign_resources(struct 
drm_crtc *crtc,
        pipe_cfg = &pstate->pipe_cfg[0];
        r_pipe_cfg = &pstate->pipe_cfg[1];

  
-	for (i = 0; i < PIPES_PER_STAGE; i++)

+       for (i = 0; i < PIPES_PER_PLANE; i++)
                pstate->pipe[i].sspp = NULL;

  
  	if (!plane_state->fb)

@@ -1240,7 +1240,7 @@ void dpu_plane_flush(struct drm_plane *plane)
                /* force 100% alpha */
                _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
        else {
-               for (i = 0; i < PIPES_PER_STAGE; i++)
+               for (i = 0; i < PIPES_PER_PLANE; i++)
                        dpu_plane_flush_csc(pdpu, &pstate->pipe[i]);
        }

  
@@ -1363,7 +1363,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane,

                        &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));

  
  	/* move the assignment here, to ease handling to another pairs later */

-       for (i = 0; i < PIPES_PER_STAGE; i++) {
+       for (i = 0; i < PIPES_PER_PLANE; i++) {
                if (!pstate->pipe[i].sspp)
                        continue;
                dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i],
@@ -1377,7 +1377,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane 
*plane,

  
  	pstate->plane_fetch_bw = 0;

        pstate->plane_clk = 0;
-       for (i = 0; i < PIPES_PER_STAGE; i++) {
+       for (i = 0; i < PIPES_PER_PLANE; i++) {
                if (!pstate->pipe[i].sspp)
                        continue;
                pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt,
@@ -1396,7 +1396,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane 
*plane)
        struct dpu_sw_pipe *pipe;
        int i;

  
-	for (i = 0; i < PIPES_PER_STAGE; i += 1) {

+       for (i = 0; i < PIPES_PER_PLANE; i += 1) {
                pipe = &pstate->pipe[i];
                if (!pipe->sspp)
                        continue;
@@ -1518,7 +1518,7 @@ static void dpu_plane_atomic_print_state(struct 
drm_printer *p,

  
  	drm_printf(p, "\tstage=%d\n", pstate->stage);
  
-	for (i = 0; i < PIPES_PER_STAGE; i++) {

+       for (i = 0; i < PIPES_PER_PLANE; i++) {
                pipe = &pstate->pipe[i];
                if (!pipe->sspp)
                        continue;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 
052fd046e8463855b16b30389c2efc67c0c15281..18ff5ec2603ed63ce45f530ced3407d3b70c737b
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -33,8 +33,8 @@
  struct dpu_plane_state {
        struct drm_plane_state base;
        struct msm_gem_address_space *aspace;
-       struct dpu_sw_pipe pipe[PIPES_PER_STAGE];
-       struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE];
+       struct dpu_sw_pipe pipe[PIPES_PER_PLANE];
+       struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE];
        enum dpu_stage stage;
        bool needs_qos_remap;
        bool pending;


























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