Hi Prabhakar, On Mon, May 12, 2025 at 07:23:21PM +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> > > The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a
I would write "5.803 MHz to 148.5 MHz" as ranges are usually expressed in increasing order. Reviewed-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com> > minimum clock check in the mode_valid callback to ensure that the clock > value does not fall below the valid range. > > Co-developed-by: Fabrizio Castro <fabrizio.castro...@renesas.com> > Signed-off-by: Fabrizio Castro <fabrizio.castro...@renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> > Reviewed-by: Biju Das <biju.das...@bp.renesas.com> > --- > v4->v5: > - No changes > > v3->v4: > - No changes > > v2->v3: > - No changes > > v1->v2: > - Added reviewed tag from Biju > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > index 4550c6d84796..ec8baecb9ba5 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -584,6 +584,9 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge > *bridge, > if (mode->clock > 148500) > return MODE_CLOCK_HIGH; > > + if (mode->clock < 5803) > + return MODE_CLOCK_LOW; > + > return MODE_OK; > } > -- Regards, Laurent Pinchart
