Hi Prabhakar, Fabrizio,
On Mon, 12 May 2025 at 20:43, Prabhakar <prabhakar.cse...@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
>
> Add clock and reset entries for the DSI and LCDC peripherals.
>
> Co-developed-by: Fabrizio Castro <fabrizio.castro...@renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro...@renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a09g057-cpg.c
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> @@ -58,6 +60,9 @@ enum clk_ids {
> CLK_SMUX2_GBE0_RXCLK,
> CLK_SMUX2_GBE1_TXCLK,
> CLK_SMUX2_GBE1_RXCLK,
> + CLK_DIV_PLLETH_LPCLK,
CLK_CDIV4_PLLETH_LPCLK?
> + CLK_CSDIV_PLLETH_LPCLK,
CLK_PLLETH_LPCLK_GEAR?
> + CLK_PLLDSI_SDIV2,
CLK_PLLDSI_GEAR?
> CLK_PLLGPU_GEAR,
>
> /* Module Clocks */
> @@ -148,6 +182,12 @@ static const struct cpg_core_clk r9a09g057_core_clks[]
> __initconst = {
> DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3,
> smux2_gbe0_rxclk),
> DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0,
> smux2_gbe1_txclk),
> DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1,
> smux2_gbe1_rxclk),
> + DEF_FIXED(".cdiv4_plleth_lpclk", CLK_DIV_PLLETH_LPCLK, CLK_PLLETH, 1,
> 4),
> + DEF_CSDIV(".plleth_lpclk_gear", CLK_CSDIV_PLLETH_LPCLK,
> CLK_DIV_PLLETH_LPCLK,
> + CSDIV0_DIVCTL2, dtable_16_128),
> +
> + DEF_PLLDSI_DIV(".plldsi_sdiv2", CLK_PLLDSI_SDIV2, CLK_PLLDSI,
".plldsi_gear", CLK_PLLDSI_GEAR ...
> + CSDIV1_DIVCTL2, dtable_2_32),
>
> DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1,
> dtable_2_64),
>
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
