Hi Prabhakar,
On Mon, 12 May 2025 at 20:43, Prabhakar <prabhakar.cse...@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
>
> The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of
> the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the
> D-PHY registers differ. Additionally, the number of resets for DSI on
> RZ/V2H(P) is two compared to three on the RZ/G2L.
>
> To accommodate these differences, a SoC-specific
> `renesas,r9a09g057-mipi-dsi` compatible string has been added for the
> RZ/V2H(P) SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlow...@linaro.org>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> @@ -14,16 +14,17 @@ description: |
> RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
> up to four data lanes.
>
> -allOf:
> - - $ref: /schemas/display/dsi-controller.yaml#
> -
> properties:
> compatible:
> - items:
> + oneOf:
> - enum:
> - - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
> - - renesas,r9a07g054-mipi-dsi # RZ/V2L
> - - const: renesas,rzg2l-mipi-dsi
> + - renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
Nit: I would add the new entry after all the old entries, to preserve
sort order (by part number).
> +
> + - items:
> + - enum:
> + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
> + - renesas,r9a07g054-mipi-dsi # RZ/V2L
> + - const: renesas,rzg2l-mipi-dsi
>
> reg:
> maxItems: 1
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
