From: Abhinav Kumar <quic_abhin...@quicinc.com>
QCS8300 support 4 streams MST and SA8775P support 2 x 2 MST. Add
support for other 3 pixels register block, and introduced
msm_dp_read_pn/msm_dp_write_pn to minimize repetitive code. All PCLK
share the same register definitions with different base addresses.
Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com>
Signed-off-by: Yongxing Mou <quic_yong...@quicinc.com>
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 128 +++++++++++++++++++++---------------
drivers/gpu/drm/msm/dp/dp_catalog.h | 18 +++--
drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 +-
drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
drivers/gpu/drm/msm/dp/dp_panel.c | 8 ++-
5 files changed, 93 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index
7b7eadb2f83b169d8df27ee93589abe05b38f3ae..d2d975805de93e929cbdadb90609b6bf3e2cf1bf
100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -60,8 +60,8 @@
#define DP_DEFAULT_AUX_SIZE 0x0200
#define DP_DEFAULT_LINK_OFFSET 0x0400
#define DP_DEFAULT_LINK_SIZE 0x0C00
-#define DP_DEFAULT_P0_OFFSET 0x1000
-#define DP_DEFAULT_P0_SIZE 0x0400
+#define DP_DEFAULT_PIXEL_OFFSET 0x1000
+#define DP_DEFAULT_PIXEL_SIZE 0x0400
struct dss_io_region {
size_t len;
@@ -72,7 +72,7 @@ struct dss_io_data {
struct dss_io_region ahb;
struct dss_io_region aux;
struct dss_io_region link;
- struct dss_io_region p0;
+ struct dss_io_region pixels[DP_STREAM_MAX];
};
struct msm_dp_catalog_private {
@@ -87,11 +87,17 @@ void msm_dp_catalog_snapshot(struct msm_dp_catalog
*msm_dp_catalog, struct msm_d
struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog,
struct msm_dp_catalog_private, msm_dp_catalog);
struct dss_io_data *dss = &catalog->io;
+ char reg_name[6];
+ int i;
msm_disp_snapshot_add_block(disp_state, dss->ahb.len, dss->ahb.base,
"dp_ahb");
msm_disp_snapshot_add_block(disp_state, dss->aux.len, dss->aux.base,
"dp_aux");
msm_disp_snapshot_add_block(disp_state, dss->link.len, dss->link.base,
"dp_link");
- msm_disp_snapshot_add_block(disp_state, dss->p0.len, dss->p0.base,
"dp_p0");
+ for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) {
+ sprintf(reg_name, "dp_p%d", i);
+ msm_disp_snapshot_add_block(disp_state, dss->pixels[i].len,
+ dss->pixels[i].base, reg_name);
+ }
}
static inline u32 msm_dp_read_aux(struct msm_dp_catalog_private *catalog, u32
offset)
@@ -124,24 +130,24 @@ static inline void msm_dp_write_ahb(struct
msm_dp_catalog_private *catalog,
writel(data, catalog->io.ahb.base + offset);
}
-static inline void msm_dp_write_p0(struct msm_dp_catalog_private *catalog,
- u32 offset, u32 data)
+static inline void msm_dp_write_pn(struct msm_dp_catalog_private *catalog,
+ enum msm_dp_stream_id stream_id, u32 offset, u32
data)
{
/*
* To make sure interface reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- writel(data, catalog->io.p0.base + offset);
+ writel(data, catalog->io.pixels[stream_id].base + offset);
}
-static inline u32 msm_dp_read_p0(struct msm_dp_catalog_private *catalog,
- u32 offset)
+static inline u32 msm_dp_read_pn(struct msm_dp_catalog_private *catalog,
+ enum msm_dp_stream_id stream_id, u32 offset)
{
/*
* To make sure interface reg writes happens before any other operation,
* this function uses writel() instread of writel_relaxed()
*/
- return readl_relaxed(catalog->io.p0.base + offset);
+ return readl_relaxed(catalog->io.pixels[stream_id].base + offset);
}
static inline u32 msm_dp_read_link(struct msm_dp_catalog_private *catalog, u32
offset)
@@ -430,8 +436,8 @@ void msm_dp_catalog_setup_peripheral_flush(struct
msm_dp_catalog *msm_dp_catalog
}
void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog,
- u32 rate, u32 stream_rate_khz,
- bool is_ycbcr_420)
+ enum msm_dp_stream_id stream_id, u32 rate,
u32 stream_rate_khz,
+ bool is_ycbcr_420)
{
u32 pixel_m, pixel_n;
u32 mvid, nvid, pixel_div = 0, dispcc_input_rate;
@@ -486,7 +492,7 @@ void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog
*msm_dp_catalog,
drm_dbg_dp(catalog->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid);
msm_dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid);
msm_dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid);
- msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_DSC_DTO, 0x0);
}
int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog
*msm_dp_catalog,
@@ -843,8 +849,9 @@ u32 msm_dp_catalog_ctrl_read_phy_pattern(struct
msm_dp_catalog *msm_dp_catalog)
}
/* panel related catalog functions */
-int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog, u32
total,
- u32 sync_start, u32 width_blanking, u32
msm_dp_active)
+int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,
+ enum msm_dp_stream_id stream_id, u32 total,
u32 sync_start,
+ u32 width_blanking, u32 msm_dp_active)
{
struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog,
struct msm_dp_catalog_private, msm_dp_catalog);
@@ -855,7 +862,7 @@ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog
*msm_dp_catalog, u32 t
msm_dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY,
width_blanking);
msm_dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active);
- reg = msm_dp_read_p0(catalog, MMSS_DP_INTF_CONFIG);
+ reg = msm_dp_read_pn(catalog, stream_id, MMSS_DP_INTF_CONFIG);
if (msm_dp_catalog->wide_bus_en)
reg |= DP_INTF_CONFIG_DATABUS_WIDEN;
@@ -865,7 +872,7 @@ int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog
*msm_dp_catalog, u32 t
DRM_DEBUG_DP("wide_bus_en=%d reg=%#x\n", msm_dp_catalog->wide_bus_en,
reg);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_CONFIG, reg);
return 0;
}
@@ -963,7 +970,8 @@ void msm_dp_catalog_panel_disable_vsc_sdp(struct
msm_dp_catalog *msm_dp_catalog)
}
void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog,
- struct drm_display_mode *drm_mode)
+ enum msm_dp_stream_id stream_id,
+ struct drm_display_mode *drm_mode)
{
struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog,
struct msm_dp_catalog_private, msm_dp_catalog);
@@ -998,45 +1006,46 @@ void msm_dp_catalog_panel_tpg_enable(struct
msm_dp_catalog *msm_dp_catalog,
display_hctl = (hsync_end_x << 16) | hsync_start_x;
- msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period *
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_VSYNC_PERIOD_F0,
vsync_period *
hsync_period);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0,
v_sync_width *
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0,
v_sync_width *
hsync_period);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0);
- msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end);
- msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
- msm_dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0);
-
- msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL,
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1,
0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_DISPLAY_HCTL,
display_hctl);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_ACTIVE_HCTL, 0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_INTF_DISPLAY_V_START_F0,
display_v_start);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_DISPLAY_V_END_F0,
display_v_end);
+ msm_dp_write_pn(catalog, stream_id, MMSS_INTF_DISPLAY_V_START_F1, 0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_DISPLAY_V_END_F1, 0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_ACTIVE_V_START_F0, 0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_ACTIVE_V_END_F0, 0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_ACTIVE_V_START_F1, 0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_ACTIVE_V_END_F1, 0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_INTF_POLARITY_CTL, 0);
+
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_TPG_MAIN_CONTROL,
DP_TPG_CHECKERED_RECT_PATTERN);
- msm_dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG,
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_TPG_VIDEO_CONFIG,
DP_TPG_VIDEO_CONFIG_BPP_8BIT |
DP_TPG_VIDEO_CONFIG_RGB);
- msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE,
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_BIST_ENABLE,
DP_BIST_ENABLE_DPBIST_EN);
- msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN,
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_TIMING_ENGINE_EN,
DP_TIMING_ENGINE_EN_EN);
drm_dbg_dp(catalog->drm_dev, "%s: enabled tpg\n", __func__);
}
-void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalog)
+void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalog,
+ enum msm_dp_stream_id stream_id)
{
struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog,
struct msm_dp_catalog_private, msm_dp_catalog);
- msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0);
- msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0);
- msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_TPG_MAIN_CONTROL, 0x0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_BIST_ENABLE, 0x0);
+ msm_dp_write_pn(catalog, stream_id, MMSS_DP_TIMING_ENGINE_EN, 0x0);
}
static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx,
size_t *len)
@@ -1051,10 +1060,11 @@ static void __iomem *msm_dp_ioremap(struct
platform_device *pdev, int idx, size_
return base;
}
-static int msm_dp_catalog_get_io(struct msm_dp_catalog_private *catalog)
+static int msm_dp_catalog_get_io(struct msm_dp_catalog_private *catalog, int
max_stream)
{
struct platform_device *pdev = to_platform_device(catalog->dev);
struct dss_io_data *dss = &catalog->io;
+ int i;
dss->ahb.base = msm_dp_ioremap(pdev, 0, &dss->ahb.len);
if (IS_ERR(dss->ahb.base))
@@ -1070,7 +1080,7 @@ static int msm_dp_catalog_get_io(struct
msm_dp_catalog_private *catalog)
* lengths based on this single region.
*/
if (PTR_ERR(dss->aux.base) == -EINVAL) {
- if (dss->ahb.len < DP_DEFAULT_P0_OFFSET +
DP_DEFAULT_P0_SIZE) {
+ if (dss->ahb.len < DP_DEFAULT_PIXEL_OFFSET +
DP_DEFAULT_PIXEL_SIZE) {
DRM_ERROR("legacy memory region not large
enough\n");
return -EINVAL;
}
@@ -1080,8 +1090,11 @@ static int msm_dp_catalog_get_io(struct
msm_dp_catalog_private *catalog)
dss->aux.len = DP_DEFAULT_AUX_SIZE;
dss->link.base = dss->ahb.base + DP_DEFAULT_LINK_OFFSET;
dss->link.len = DP_DEFAULT_LINK_SIZE;
- dss->p0.base = dss->ahb.base + DP_DEFAULT_P0_OFFSET;
- dss->p0.len = DP_DEFAULT_P0_SIZE;
+ for (i = DP_STREAM_0; i < max_stream; i++) {
+ dss->pixels[i].base =
+ dss->ahb.base + (i + 1) *
DP_DEFAULT_PIXEL_OFFSET;
+ dss->pixels[i].len = DP_DEFAULT_PIXEL_SIZE;
+ }
} else {
DRM_ERROR("unable to remap aux region: %pe\n",
dss->aux.base);
return PTR_ERR(dss->aux.base);
@@ -1093,17 +1106,26 @@ static int msm_dp_catalog_get_io(struct
msm_dp_catalog_private *catalog)
return PTR_ERR(dss->link.base);
}
- dss->p0.base = msm_dp_ioremap(pdev, 3, &dss->p0.len);
- if (IS_ERR(dss->p0.base)) {
- DRM_ERROR("unable to remap p0 region: %pe\n",
dss->p0.base);
- return PTR_ERR(dss->p0.base);
+ dss->pixels[0].base = msm_dp_ioremap(pdev, 3,
&dss->pixels[0].len);
+ if (IS_ERR(dss->pixels[0].base)) {
+ DRM_ERROR("unable to remap p0 region: %pe\n",
dss->pixels[0].base);
+ return PTR_ERR(dss->pixels[0].base);
+ }
+
+ for (i = DP_STREAM_1; i < max_stream; i++) {
+ /* pixels clk reg index start from 3*/
+ dss->pixels[i].base = msm_dp_ioremap(pdev, i + 3,
&dss->pixels[i].len);
+
+ if (IS_ERR(dss->pixels[i].base))
+ DRM_DEBUG_DP("unable to remap p%d region:
%pe\n", i,
+ dss->pixels[i].base);
}
}
return 0;
}
-struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev)
+struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev, int max_stream)
{
struct msm_dp_catalog_private *catalog;
int ret;
@@ -1114,7 +1136,7 @@ struct msm_dp_catalog *msm_dp_catalog_get(struct device
*dev)
catalog->dev = dev;
- ret = msm_dp_catalog_get_io(catalog);
+ ret = msm_dp_catalog_get_io(catalog, max_stream);
if (ret)
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h
b/drivers/gpu/drm/msm/dp/dp_catalog.h
index
f9e7506afcf4f4d932665462ca316f6c66c662a6..9bfb83873ce8749bec173a2bc2366c429f91354a
100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -67,8 +67,9 @@ void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog
*msm_dp_catalog, bo
void msm_dp_catalog_ctrl_psr_mainlink_enable(struct msm_dp_catalog
*msm_dp_catalog, bool enable);
void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog
*msm_dp_catalog);
void msm_dp_catalog_ctrl_config_misc(struct msm_dp_catalog *msm_dp_catalog,
u32 cc, u32 tb);
-void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog, u32
rate,
- u32 stream_rate_khz, bool is_ycbcr_420);
+void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog,
+ enum msm_dp_stream_id stream_id, u32 rate,
u32 stream_rate_khz,
+ bool is_ycbcr_420);
int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog
*msm_dp_catalog, u32 pattern);
u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog);
void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog);
@@ -93,15 +94,18 @@ void msm_dp_catalog_ctrl_send_phy_pattern(struct
msm_dp_catalog *msm_dp_catalog,
u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog
*msm_dp_catalog);
/* DP Panel APIs */
-int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog, u32
total,
- u32 sync_start, u32 width_blanking, u32
msm_dp_active);
+int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog,
+ enum msm_dp_stream_id stream_id, u32 total,
u32 sync_start,
+ u32 width_blanking, u32 msm_dp_active);
void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog
*msm_dp_catalog, struct dp_sdp *vsc_sdp);
void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog
*msm_dp_catalog);
void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog,
- struct drm_display_mode *drm_mode);
-void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalog);
+ enum msm_dp_stream_id stream_id,
+ struct drm_display_mode *drm_mode);
+void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalog,
+ enum msm_dp_stream_id stream_id);
-struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev);
+struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev, int max_stream);
/* DP Audio APIs */
void msm_dp_catalog_write_audio_stream(struct msm_dp_catalog *msm_dp_catalog,
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index
7db23968c4227557d3cea9bfbf5aa3c3e17a87d8..594dd6fe9381403b8ab085441276d2ce26612efe
100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -2075,7 +2075,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl
*msm_dp_ctrl, struct msm_dp_panel *
msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel);
- msm_dp_catalog_ctrl_config_msa(ctrl->catalog,
+ msm_dp_catalog_ctrl_config_msa(ctrl->catalog, msm_dp_panel->stream_id,
ctrl->link->link_params.rate,
pixel_rate_orig,
msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420);
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index
a13e4007858701787562eded7b6fc8f7171e167b..76d07685f5a89109723b68ba9d97c0b0332b18aa
100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -748,7 +748,7 @@ static int msm_dp_init_sub_modules(struct
msm_dp_display_private *dp)
goto error;
}
- dp->catalog = msm_dp_catalog_get(dev);
+ dp->catalog = msm_dp_catalog_get(dev, dp->max_stream);
if (IS_ERR(dp->catalog)) {
rc = PTR_ERR(dp->catalog);
DRM_ERROR("failed to initialize catalog, rc = %d\n", rc);
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c
b/drivers/gpu/drm/msm/dp/dp_panel.c
index
d9041e235104a74b3cc50ff2e307eae0c4301ef3..fb9216673f0d39d10af864346ebfa884dbe1f499
100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -285,12 +285,13 @@ void msm_dp_panel_tpg_config(struct msm_dp_panel
*msm_dp_panel, bool enable)
}
if (!enable) {
- msm_dp_catalog_panel_tpg_disable(catalog);
+ msm_dp_catalog_panel_tpg_disable(catalog,
msm_dp_panel->stream_id);
return;
}
drm_dbg_dp(panel->drm_dev, "calling catalog tpg_enable\n");
- msm_dp_catalog_panel_tpg_enable(catalog,
&panel->msm_dp_panel.msm_dp_mode.drm_mode);
+ msm_dp_catalog_panel_tpg_enable(catalog, msm_dp_panel->stream_id,
+ &msm_dp_panel->msm_dp_mode.drm_mode);
}
static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel
*msm_dp_panel)
@@ -395,7 +396,8 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel
*msm_dp_panel)
msm_dp_active = data;
- msm_dp_catalog_panel_timing_cfg(catalog, total, sync_start,
width_blanking, msm_dp_active);
+ msm_dp_catalog_panel_timing_cfg(catalog, msm_dp_panel->stream_id,
total, sync_start,
+ width_blanking, msm_dp_active);
if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420)
msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel);
--
2.34.1
