From: Abhinav Kumar <quic_abhin...@quicinc.com>

Add support to program the MST enabled bit in the mainlink
control when a mst session is active and disabled.

Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com>
Signed-off-by: Yongxing Mou <quic_yong...@quicinc.com>
---
 drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++
 drivers/gpu/drm/msm/dp/dp_catalog.h |  1 +
 drivers/gpu/drm/msm/dp/dp_ctrl.c    |  4 ++++
 drivers/gpu/drm/msm/dp/dp_reg.h     |  1 +
 4 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c 
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 
e6920008356991ad0c023664d5e286433ccf5d0b..ff0fb742d122646dd45fcd868a61532c630419d1
 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -407,6 +407,23 @@ void msm_dp_catalog_ctrl_psr_mainlink_enable(struct 
msm_dp_catalog *msm_dp_catal
        msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, val);
 }
 
+void msm_dp_catalog_mst_config(struct msm_dp_catalog *msm_dp_catalog, bool 
enable)
+{
+       struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog,
+                                                             struct 
msm_dp_catalog_private,
+                                                             msm_dp_catalog);
+
+       u32 mainlink_ctrl;
+
+       mainlink_ctrl = msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
+       if (enable)
+               mainlink_ctrl |= DP_MAINLINK_CTRL_MST_EN;
+       else
+               mainlink_ctrl &= ~DP_MAINLINK_CTRL_MST_EN;
+
+       msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
+}
+
 void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catalog,
                                                bool enable)
 {
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h 
b/drivers/gpu/drm/msm/dp/dp_catalog.h
index 
88ef98c9b0cb2d273a0c190ff7b2783b5e254937..e2c5e0235834527998d40caddd1649b434e1f180
 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -130,5 +130,6 @@ void msm_dp_catalog_audio_sfe_level(struct msm_dp_catalog 
*catalog, u32 safe_to_
 /* DP MST APIs */
 void msm_dp_catalog_trigger_act(struct msm_dp_catalog *dp_catalog);
 bool msm_dp_catalog_read_act_complete_sts(struct msm_dp_catalog *dp_catalog);
+void msm_dp_catalog_mst_config(struct msm_dp_catalog *dp_catalog, bool enable);
 
 #endif /* _DP_CATALOG_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 
0088fefd88e517e01bb66f02661c877173181d8a..64d9862841a22b8298c6e4eb6e488834e38ddcd0
 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -184,6 +184,9 @@ static void msm_dp_ctrl_configure_source_params(struct 
msm_dp_ctrl_private *ctrl
        msm_dp_catalog_ctrl_lane_mapping(ctrl->catalog);
        msm_dp_catalog_setup_peripheral_flush(ctrl->catalog);
 
+       if (ctrl->mst_active)
+               msm_dp_catalog_mst_config(ctrl->catalog, true);
+
        msm_dp_ctrl_config_ctrl(ctrl, msm_dp_panel);
 
        tb = msm_dp_link_get_test_bits_depth(ctrl->link,
@@ -2167,6 +2170,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl)
        phy = ctrl->phy;
 
        msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
+       msm_dp_catalog_mst_config(ctrl->catalog, false);
 
        ctrl->mst_active = false;
 
diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
index 
b993487925dbd78e8f78e09fbf52ab38f268b71a..f079c1132d5aa9a97a0bef314e31f64977d7ffc4
 100644
--- a/drivers/gpu/drm/msm/dp/dp_reg.h
+++ b/drivers/gpu/drm/msm/dp/dp_reg.h
@@ -109,6 +109,7 @@
 #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP      
FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1)
 #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE       
FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3)
 #define DP_MAINLINK_FB_BOUNDARY_SEL            (0x02000000)
+#define DP_MAINLINK_CTRL_MST_EN                        (0x04000100)
 
 #define REG_DP_STATE_CTRL                      (0x00000004)
 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1   (0x00000001)

-- 
2.34.1

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