[PATCH 1/2] drm/etnaviv: reset bit 0 when disabling pulse eater for reset

[Lucas Stach]

It seems this bit is sticky across the reset. The downstream driver
pulses this bit on and off in the reset sequence, which had been
missed when porting this part over from the Vivante driver.

While no bad behavior has been observed when the bit is active after
reset, better be safe than sorry and copy this part verbatim.

Fixes: b0da08559c74 ("drm/etnaviv: disable MLCG and pulse eater on GPU reset")
Signed-off-by: Lucas Stach <l.st...@pengutronix.de>
---
 drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c 
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index cf0d9049bcf1..bf59f4ee0e72 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -550,6 +550,8 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
                gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
                pulse_eater |= BIT(0);
                gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
+               pulse_eater &= ~BIT(0);
+               gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 
                /* enable clock */
                control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
-- 
2.39.5